4.1 Introduction

4.2 H.110 Clock Configuration Example

Program

4.1 Introduction

The boards in a CT bus (MVIP-95, H.100, H.110) system are synchronized using clocks. In a system, one board drives the bus clock signals. All other boards reference their clocks from the bus.

On the MVIP-95 bus, H.100 bus, and H.110 bus, the board that drives the bus clocks is the MVIP clock master. In a digital system, the MVIP clock master derives the bus clock signals from the digital trunk's high-quality timing references. In an analog system with no digital telephone network interfaces, a board is configured as the MVIP bus clock master using the on-board oscillator to drive the clock signals.

The H.100 bus has a secondary clock signal that can be configured as a backup clock reference. On the H.100 bus, this clock signal is CT_NETREF. The H.110 bus has two secondary clock signals that can be configured as a backup clock reference: CT_NETREF_1 and CT_NETREF_2.

Note: CT_NETREF and CT_NETREF_1 are the same physical signal.

The H.100 bus and the H.110 bus can be configured to have a backup secondary clock master to which a clock fallback can occur. To configure the clock source for clock fallback, see swiConfigBoardClock. For further information about configuring clocks on the H.100 bus and H.110 bus, see the ECTF H.100 Hardware Compatibility Specification: CT Bus R1.0 and the ECTF H.110 Hardware Compatibility Specification: CT Bus R1.0.

In a multi-chassis MVIP system, all the boards in the PC chassis must be driven by the same clock source. One H bus (H.100 or H.110) in the system must be configured as the H bus clock master, driving the H bus clock signals. The H bus in each PC chassis is then configured to drive the MVIP bus in their chassis.

The Switching service provides functions to allow you to control the clocks on the underlying MVIP switching device. It provides functions for configuring the:

• Board's clock source (H bus or network).

• Secondary clock signal on the bus.

The following table lists when to use the clock configuration functions available in the Switching service:

If you want to...	Then use...
Establish the clock source for an MVIP board	swiConfigBoardClock
Define the source of the NETREF clocks on the H.100/H.110 bus	swiConfigNetrefClock
Retrieve information regarding the configuration of the board clocking and current status of the clocks	swiGetBoardClock
Retrieve the status of a potential TDM bus clock timing reference	swiGetTimingReference

Refer to Getting Started With MVIP Switching for more information about clocking.

The following section provides an example of clock configuration using swiConfigBoardClock and swiConfigNetrefClock on CompactPCI AG Quad boards.

4.2 H.110 Clock Configuration Example

In this example, there are four CompactPCI AG Quad boards in the system. The first board is the primary master that drives the H.110 A clock from the PSTN network connection. The second board is the secondary master that drives the H.110 B clock from the H.110 A clock. It has a PSTN network connection that it uses as an alternate clock source when a fallback to the B clock occurs. The third board drives the NETREF_1 signal from its own PSTN network connection, and the fourth board similarly drives NETREF_2. This example of clock fallback is shown in Figure 4.

If the primary clock master fails, fallback to a secondary master (B clock) can be programmed to be automatic. In this example, the secondary master uses its own PSTN interface to drive the B clocks. It can also be programmed to use either of the NETREF signals if so desired.

This example:

• Configures the board clock of the first CompactPCI AG Quad board to synchronize to the PSTN clocks and become the H.110 A clock master.

• Configures the board clock of the second CompactPCI AG Quad board to synchronize to the A clocks and become the H.110 B clock master. Its fallback source is its network connection.

• Configures the third and fourth boards to slave off the A clocks.

• Configures the third and fourth boards to drive NETREF_1 and NETREF_2 respectively.

• Sets the automatic fallback feature to allow for a fallback from the Primary to the Secondary Master.

For more information about H.110 A clocks and B clocks, see the ECTF: H.110 Revision 1.0 Hardware Compatibility Specification: CT Bus.

Figure 4. Clock Fallback and Network Synchronization

Program

1. Configure the board clock of the first CompactPCI AG Quad to synchronize to the PSTN clocks and become the primary clock master (A clock).

       SWI_CLOCK_ARGS boardclock;
   
       /* Make first board sync off the PSTN digital trunk 1 */
       boardclock.size = sizeof(SWI_CLOCK_ARGS);
       boardclock.clocktype = MVIP95_H100_CLOCKING;
       boardclock.clocksource = MVIP95_SOURCE_NETWORK;
       boardclock.network = 1;
     boardclock.ext.h100.h100clockmode= MVIP95_H100_MASTER_A;
        boardclock.ext.h100.autofallback= MVIP95_H100_ENABLE_AUTO_FB;
        boardclock.ext.h100.netrefclockspeed= MVIP95_H100_NETREF_8KHZ;
     boardclock.ext.h100.fallbackclocksource= MVIP95_SOURCE_NETWORK;
     boardclock.ext.h100.fallbacknetwork = 2;
   
       swiConfigBoardClock(firstt1, &boardclock);
   
   

2. Configure the board clock of the second CompactPCI AG Quad board to synchronize to the PSTN clocks and become the secondary clock master (B clock).

       SWI_CLOCK_ARGS boardclock;
   
       boardclock.size = sizeof(SWI_CLOCK_ARGS);
       boardclock.clocktype = MVIP95_H100_CLOCKING;
       boardclock.clocksource = MVIP95_SOURCE_H100_A;
       boardclock.network = 0;
     boardclock.ext.h100.h100clockmode= MVIP95_H100_MASTER_B;
        boardclock.ext.h100.autofallback= MVIP95_H100_ENABLE_AUTO_FB;
        boardclock.ext.h100.netrefclockspeed= MVIP95_H100_NETREF_8KHZ;
     boardclock.ext.h100.fallbackclocksource= MVIP95_SOURCE_NETWORK;
     boardclock.ext.h100.fallbacknetwork = 1;
   
       swiConfigBoardClock(secondt1, &boardclock);
   
   

3. Configure the board clocks of the third and fourth CompactPCI AG Quad boards to slave to the H.110 A clocks.

       SWI_CLOCK_ARGS boardclock3;
       SWI_CLOCK_ARGS boardclock4;
   
   
       boardclock3.size = sizeof(SWI_CLOCK_ARGS);
       boardclock3.clocktype = MVIP95_H100_CLOCKING;
       boardclock3.clocksource = MVIP95_SOURCE_H100_A;
       boardclock3.network = 0;
     Boardclock3.ext.h100.h100clockmode= MVIP95_H100_SLAVE;
        boardclock3.ext.h100.autofallback= MVIP95_H100_ENABLE_AUTO_FB;
        boardclock3.ext.h100.netrefclockspeed= MVIP95_H100_NETREF_8KHZ;
     
       boardclock4.size = sizeof(SWI_CLOCK_ARGS);
       boardclock4.clocktype = MVIP95_H100_CLOCKING;
       boardclock4.clocksource = MVIP95_SOURCE_H100_A;
       boardclock4.network = 0;
     boardclock4.ext.h100.h100clockmode= MVIP95_H100_SLAVE;
        boardclock4.ext.h100.autofallback= MVIP95_H100_ENABLE_AUTO_FB;
        boardclock4.ext.h100.netrefclockspeed= MVIP95_H100_NETREF_8KHZ;
     
   
       swiConfigBoardClock(thirdt1, &boardclock3);
       swiConfigBoardClock(fourtht1, &boardclock4);
   
   

4. Configure the third and fourth CompactPCI AG Quad boards to drive the NETREF_1 and NETREF_2 signals on the H.110 bus from their PSTN connection.

     SWI_NETREF_CLOCK_ARGS       netref_1;
     SWI_NETREF_CLOCK_ARGS       netref_2;
   
     netref_1.size = sizeof(SWI_NETREF_CLOCK_ARGS);
     netref_1.network = 1;
     netref_1.netref_clock_mode = MVIP95_H100_NETREF_1;
     netref_1.netref_clock_speed = MVIP95_H100_NETREF_8KHZ;
   
   
     netref_2.size = sizeof(SWI_NETREF_CLOCK_ARGS);
     netref_2.network = 1;
     netref_2.netref_clock_mode = MVIP95_H100_NETREF_2;
     netref_2.netref_clock_speed = MVIP95_H100_NETREF_8KHZ;
   
     swiConfigNetrefClock(thirdt1, netref_1);
     swiConfigNetrefClock(fourtht1, netref_2);