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Chapter 5

Configuring Board Clocking

5.1 Introduction

5.2 Clocking Models

5.3 H.100/H.110 Bus Clocking

5.3.1 H.100/H.110 Clocking Overview

5.3.2 QX 2000/100-4L Clocking Restrictions

5.3.3 Configuring QX 2000/100-4L Board Clocking

5.3.4 Examples

: Example 1: System With Analog and Digital Boards, Digital Board is Master
: Example 2: System With Analog Boards Only, QX is Master

5.4 MVIP-90 Clocking

: 5.4.1 MVIP-90 Clocking Overview
: 5.4.2 QX 2000/80-4L Clocking Restrictions
: 5.4.3 Configuring QX 2000/80-4L Board Clocking

5.5 Choosing a Clock Master

5.1 Introduction

When multiple boards are connected to the CT bus, you can set up a bus clock to synchronize timing between them. This section: Provides a brief overview of H bus clocking, and describes how to configure clocking for QX boards on the H.100 bus. Provides a brief overview of MVIP-90 clocking, and describes how to configure clocking for QX boards on the MVIP bus.
For more information on clock configuration, refer to the Getting Started with MVIP Switching manual. For more information on retrieving and setting OAM keyword values, refer to the OAM System User's Manual.

5.2 Clocking Models

There are three different models for board clocking configuration: MVIP-90/H-MVIP H.100 H.110
The following table shows the clocking models appropriate for each QX type: Board Type Clocking Models QX 2000/80-4L MVIP-90/H-MVIP QX 2000/100-4L H.100
You can determine the clocking model appropriate for a QX board by retrieving the value of the Clocking.Type keyword. For example:
Clocking.Type = Hbus

Board Type	Clocking Models
QX 2000/80-4L	MVIP-90/H-MVIP
QX 2000/100-4L	H.100

5.3 H.100/H.110 Bus Clocking

Since the QX 2000 board provides only analog interfaces to an external network, it cannot use an external source to derive a timing reference. Therefore, the board does not support all of the modes and roles available to digital interface boards. This section provides a brief overview of H.100/H.110 bus clocking, lists the rules and restrictions for QX 2000 boards, and describes how to configure clocking for the QX board.

5.3.1 H.100/H.110 Clocking Overview

Most boards connected on an H.100 or H.110 bus can be configured in any of the following modes: Board Mode Description Primary clock master Drives a clock signal (either A_CLOCK or B_CLOCK) for boards connected to the CT bus. The signal it uses is derived from timing references, usually from external sources such as digital trunks. It can switch between two specified timing sources in order to maintain the clock signal. If both of its timing references fail, the primary clock master stopped providing the clock signal. The secondary clock master then provides bus synchronization. Secondary clock master Drives the clock signal not driven by the primary master (for example, if the primary master drives A_CLOCK, the secondary master drives B_CLOCK). The signal it uses is derived from the clock driven by the primary master. If this signal fails, the secondary master continues to drive its clock using another clock source as its timing reference. Clock slave References its timing from the primary clock master. Can use the secondary clock master as a fallback source of clock timing. Standalone Does not reference the primary or secondary master, and consequently may not make switch connections to the CT bus.
Clock masters (primary or secondary) can synchronize their own timing signals from the following sources: Timing Reference Source Description NETWORK A signal originating within the public network, and entering the system through a digital trunk. NETREF A clock signal broadcast on the bus by another device, which can be used by a clock master as a timing reference from which to synchronize A_CLOCK or B_CLOCK. NETREF2 (H.110 only) A secondary NETREF signal. OSC A signal originating from a board's oscillator.
For more information about configuring bus clocks, refer to the OAM System User's Manual or the ECTF H.110 Hardware Compatibility Specification: CT Bus R1.0.

Board Mode	Description
Primary clock master	Drives a clock signal (either A_CLOCK or B_CLOCK) for boards connected to the CT bus. The signal it uses is derived from timing references, usually from external sources such as digital trunks. It can switch between two specified timing sources in order to maintain the clock signal. If both of its timing references fail, the primary clock master stopped providing the clock signal. The secondary clock master then provides bus synchronization.
Secondary clock master	Drives the clock signal not driven by the primary master (for example, if the primary master drives A_CLOCK, the secondary master drives B_CLOCK). The signal it uses is derived from the clock driven by the primary master. If this signal fails, the secondary master continues to drive its clock using another clock source as its timing reference.
Clock slave	References its timing from the primary clock master. Can use the secondary clock master as a fallback source of clock timing.
Standalone	Does not reference the primary or secondary master, and consequently may not make switch connections to the CT bus.

Timing Reference Source	Description
NETWORK	A signal originating within the public network, and entering the system through a digital trunk.
NETREF	A clock signal broadcast on the bus by another device, which can be used by a clock master as a timing reference from which to synchronize A_CLOCK or B_CLOCK.
NETREF2	(H.110 only) A secondary NETREF signal.
OSC	A signal originating from a board's oscillator.

5.3.2 QX 2000/100-4L Clocking Restrictions

The following limitations apply to setting up CT bus clocking with QX 2000/100-4L boards: Since the QX 2000 board provides only analog interfaces to an external network, it cannot use an external source directly to derive a timing reference. Thus the NETWORK timing reference is not available. The only timing source available to the QX 2000 board is OSC¹. Since the QX 2000 board is a PCI board, it is H.100-compatible, not H.110- compatible. Thus the NETREF2 signal is not available. The QX 2000 board cannot drive B_CLOCK, or take its timing reference from B_CLOCK. The QX 2000 board cannot operate in standalone mode.
If another board has access to an outside clock signal (for example, a digital board attached to a T1 or E1 trunk), you should make this board the clock master. A QX board should be used as clock master only if none of the boards on the H.100/H.110 bus have any access to an outside digital clock signal (for example, if your system contains only boards with analog trunk interfaces). In this case, the QX board can drive A_CLOCK using its internal oscillator (OSC) as the timing reference.
For more information about choosing a clock master, see Section 5.5.
A QX board cannot serve as secondary master, or switch to the secondary master if the primary master stops driving the clock. This is because a QX board cannot drive B_CLOCK, or take a timing reference from B_CLOCK.

5.3.3 Configuring QX 2000/100-4L Board Clocking

To configure QX 2000/100-4L clocking, set the following keywords for each board: Clocking.HBus.ClockSource -- Specifies the source from which a board derives its timing. Clocking.HBus.ClockMode -- Specifies the CT bus clock mode for the board (for example, A_CLOCK master, B_CLOCK master, slave or standalone).
For each board, set the keywords as follows: Keyword To configure QX as primary master, set to... To configure QX as slave, set to... Clocking.HBus.ClockSource OSC¹ A_CLOCK Clocking.HBus.ClockMode MASTER_A SLAVE to indicate that the board does not drive any CT bus clock. ¹ You can also set this keyword to NETREF. However, you should use this setting only if another board has access to an external timing reference, and the QX board must act as clock master. This configuration is not recommended. The QX board automatically falls back to OSC if NETREF fails. Note: A QX board cannot be configured as secondary clock master.

Keyword	To configure QX as primary master, set to...	To configure QX as slave, set to...
Clocking.HBus.ClockSource	`OSC¹`	`A_CLOCK`
Clocking.HBus.ClockMode	`MASTER_A`	`SLAVE` to indicate that the board does not drive any CT bus clock.

5.3.4 Examples

Example 1: System With Analog and Digital Boards, Digital Board is Master

The following example assumes a system configuration where two QX boards and one AG 4000 board reside on a single chassis. The boards are configured in the following way: Board Configuration Board 0 AG 4000. Primary bus master. Drives A_CLOCK, based on signal from digital trunk. Auto fallback enabled Board 1 QX board. Clock slave to A_CLOCK. Falls back to OSC. Board 2 QX board. Clock slave to A_CLOCK. Falls back to OSC.
Figure 18 illustrates this configuration: Figure 17. Sample Board Clocking Configuration
The following table shows keywords used to configure the boards according to the configuration shown in Figure 18. Board Role Clocking Keyword Settings 0 AG 4000, primary clock master Clocking.HBus.ClockMode = MASTER_A Clocking.HBus.ClockSource = NETWORK Clocking.HBus.AutoFallBack = YES Clocking.HBus.FallBackClockSource = NETWORK Clocking.HBus.ClockSourceNetwork = 2 Clocking.HBus.FallBackNetwork = 3 1 QX, clock slave Clocking.HBus.ClockMode = SLAVE Clocking.HBus.ClockSource = A_CLOCK 2 QX, clock slave Clocking.HBus.ClockMode = SLAVE Clocking.HBus.ClockSource = A_CLOCK
In this configuration, Board 0 is the primary clock master and drives A_CLOCK. All slave boards on the system use A_CLOCK as their first timing reference. Board 0 references its timing from a network timing signal derived from a NETWORK signal from trunk 2. If the signal on trunk 2 should fail, Board 0 falls back to the signal from trunk 3.
If Board 0 stops driving the clock entirely, all slave boards fall back to their oscillators.

Board	Configuration
Board 0	AG 4000. Primary bus master. Drives A_CLOCK, based on signal from digital trunk. Auto fallback enabled
Board 1	QX board. Clock slave to A_CLOCK. Falls back to OSC.
Board 2	QX board. Clock slave to A_CLOCK. Falls back to OSC.

Board	Role	Clocking Keyword Settings
0	AG 4000, primary clock master	`Clocking.HBus.ClockMode = MASTER_A` `Clocking.HBus.ClockSource = NETWORK` `Clocking.HBus.AutoFallBack = YES` `Clocking.HBus.FallBackClockSource = NETWORK` `Clocking.HBus.ClockSourceNetwork = 2` `Clocking.HBus.FallBackNetwork = 3`
1	QX, clock slave	`Clocking.HBus.ClockMode = SLAVE` `Clocking.HBus.ClockSource = A_CLOCK`
2	QX, clock slave	`Clocking.HBus.ClockMode = SLAVE` `Clocking.HBus.ClockSource = A_CLOCK`

Example 2: System With Analog Boards Only, QX is Master

The following example assumes a system configuration where four QX boards reside on a single chassis. The boards are configured in the following way: Board Configuration Board 0 Primary bus master. Drives A_CLOCK, based on signal from internal oscillator. Auto fallback enabled Board 1 Clock slave to A_CLOCK (auto fallback enabled) Board 2 Clock slave to A_CLOCK (auto fallback enabled) Board 3 Clock slave to A_CLOCK (auto fallback enabled)
Figure 18 illustrates this configuration: Figure 18. Sample Board Clocking Configuration
The following table shows keywords used to configure the boards according to the configuration shown in Figure 18. Board Role Clocking Keyword Settings 0 Primary clock master Clocking.HBus.ClockMode = MASTER_A Clocking.HBus.ClockSource = OSC 1 Clock slave Clocking.HBus.ClockMode = SLAVE Clocking.HBus.ClockSource = A_CLOCK 2 Clock slave Clocking.HBus.ClockMode = SLAVE Clocking.HBus.ClockSource = A_CLOCK 3 Clock slave Clocking.HBus.ClockMode = SLAVE Clocking.HBus.ClockSource = A_CLOCK
In this configuration, Board 0 is the primary master and drives A_CLOCK. All slave boards on the system use A_CLOCK as their first timing reference. Board 0 references its timing from a signal derived from its oscillator. If Board 0 stops driving the clock, all boards fall back to their oscillators.

Board	Configuration
Board 0	Primary bus master. Drives A_CLOCK, based on signal from internal oscillator. Auto fallback enabled
Board 1	Clock slave to A_CLOCK (auto fallback enabled)
Board 2	Clock slave to A_CLOCK (auto fallback enabled)
Board 3	Clock slave to A_CLOCK (auto fallback enabled)

Board	Role	Clocking Keyword Settings
0	Primary clock master	`Clocking.HBus.ClockMode = MASTER_A` `Clocking.HBus.ClockSource = OSC`
1	Clock slave	`Clocking.HBus.ClockMode = SLAVE` `Clocking.HBus.ClockSource = A_CLOCK`
2	Clock slave	`Clocking.HBus.ClockMode = SLAVE` `Clocking.HBus.ClockSource = A_CLOCK`
3	Clock slave	`Clocking.HBus.ClockMode = SLAVE` `Clocking.HBus.ClockSource = A_CLOCK`

5.4 MVIP-90 Clocking

Since the QX 2000 board provides only analog interfaces to an external network, it cannot use an external source to derive a timing reference. Therefore, the board does not support all of the modes and roles available to digital interface boards. This section provides a brief overview of MVIP-90 bus clocking, lists the rules and restrictions for QX 2000 boards, and describes how to configure clocking for the QX board.

5.4.1 MVIP-90 Clocking Overview

Each board connected on an MVIP-90 bus can be configured in one of the following modes: Board Mode Description Clock master Drives the primary timing reference for boards connected to the CT bus. It can switch between two specified timing sources in order to maintain the timing reference. Clock slave References its timing from the clock master. Standalone Does not reference the clock master, and consequently may not make switch connections to the MVIP bus.
Boards that act as clock slaves derive their timing from signals driven by the clock master. The clock master can synchronize its own timing signals from the following sources: Timing Reference Source Description OSC A signal originating from a board's oscillator. SEC8K A clock signal broadcast on the bus by another device, which can be used by a clock master as a timing reference from which to synchronize the bus clock.

Board Mode	Description
Clock master	Drives the primary timing reference for boards connected to the CT bus. It can switch between two specified timing sources in order to maintain the timing reference.
Clock slave	References its timing from the clock master.
Standalone	Does not reference the clock master, and consequently may not make switch connections to the MVIP bus.

Timing Reference Source	Description
OSC	A signal originating from a board's oscillator.
SEC8K	A clock signal broadcast on the bus by another device, which can be used by a clock master as a timing reference from which to synchronize the bus clock.

5.4.2 QX 2000/80-4L Clocking Restrictions

The following limitations apply to setting up CT bus clocking with QX 2000/80-4L boards: Since the QX 2000 board provides only analog interfaces to an external network, it cannot use an external source directly to derive a timing reference. Thus only OSC is available as a timing reference². The QX 2000 board cannot operate in standalone mode.
If another board has access to an outside clock signal (for example, a digital board attached to a T1 or E1 trunk), you should make this board the clock master. A QX board should be used as clock master only if none of the boards on the MVIP bus have any access to an outside digital clock signal (for example, if your system contains only boards with analog trunk interfaces). In this case, the QX board can drive the clock using its internal oscillator (OSC) as the timing reference.
For more information about choosing a clock master, see Section 5.5.

5.4.3 Configuring QX 2000/80-4L Board Clocking

To configure QX 2000/80-4L clocking, set the Clocking.HBus.ClockSource keyword for each board. This keyword specifies the CT bus clock mode for the board (master or slave).
For each board, set the keywords as follows: Keyword To configure QX as primary master, set to... To configure QX as slave, set to... Clocking.MVIP.ClockRef OSC¹ MVIP

Keyword	To configure QX as primary master, set to...	To configure QX as slave, set to...
Clocking.MVIP.ClockRef	`OSC`¹	`MVIP`

5.5 Choosing a Clock Master

When choosing which boards that act as primary and secondary clock masters in a mixed-board system, use the following priority system: AG 4000 AG Quad AG 2000 QX 2000
For example, if a system includes two AG 4000 boards and several other NMS boards, the AG 4000 boards should be configured as the system's primary and secondary clock masters. If the system includes one AG 4000 board, one AG Quad board, and several other boards, the AG 4000 board should be configured as the system primary clock master and the AG Quad as the system secondary clock master. Note: QX boards cannot fall back to the secondary clock master.
Following this priority system ensures the most reliable performance when CT bus clock fallback occurs.

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¹ It is also possible to configure a QX board to use NETREF as a timing reference. However, in this case you should make the QX board a slave, and use the board which would otherwise drive NETREF as the clock master.

² It is also possible to configure a QX board to use SEC8K as a timing reference. However, in this case you should make the QX board a slave, and use the board which would otherwise drive SEC8K as the clock master. If SEC8K is used as the timing reference, the board falls back to OSC if SEC8K fails.

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