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Chapter 6

QX 2000 Board Switching

: 6.1 Introduction
: 6.2 QX 2000/100-4L MVIP-95 Switch Model
: 6.3 QX 2000/80-4L MVIP-95 Switch Model
: 6.4 QX 2000/80-4L MVIP-90 Switch Model
: 6.5 Default MVIP Switch Connections
: 6.6 Mapping MVIP-95 to MVIP-90
: 6.7 FMIC Switching Restrictions
: 6.8 MVIP-90/H Bus Interoperability

6.1 Introduction

This chapter: Describes the QX 2000 board MVIP switch models Describes how analog trunks are automatically routed to DSP resources if switching is not enabled Explains how you can change this default routing by enabling MVIP switching
The QX 2000/80-4L board is compatible with both the MVIP-90 and MVIP-95 switch models. The QX 2000/100-4L board is compatible with the MVIP-95 switch model only. The QX 2000 switch block is controlled by the Natural Access Switching service.

6.2 QX 2000/100-4L MVIP-95 Switch Model

Figure 19 shows the QX 2000 MVIP-95 switch model. The specific use of each stream is as follows:

H.100 Bus Streams

H.100 bus

Streams 0..32, timeslots 0..128

Local Bus Streams

Trunk voice information

Analog Trunk 1: Streams 0 and 1, timeslot 0
Analog Trunk 2: Streams 0 and 1, timeslot 1
Analog Trunk 3: Streams 0 and 1, timeslot 2
Analog Trunk 4: Streams 0 and 1, timeslot 3

Trunk signaling information

Analog Trunk 1: Streams 2 and 3, timeslot 0
Analog Trunk 2: Streams 2 and 3, timeslot 1
Analog Trunk 3: Streams 2 and 3, timeslot 2
Analog Trunk 4: Streams 2 and 3, timeslot 3

DSP voice information

Streams 4 and 5, timeslots 0..3

DSP signaling information

Streams 6 and 7, timeslots 0..3

Local telephone voice

Streams 8 and 9, timeslot 0

Local telephone signaling

Streams 10 and 11, timeslot 0

Audio interface

Streams 12 and 13, timeslot 0
Figure 19. QX 2000/100-4L Switch Model

H.100 Bus Streams
H.100 bus	Streams 0..32, timeslots 0..128

Local Bus Streams
Trunk voice information	Analog Trunk 1: Streams 0 and 1, timeslot 0 Analog Trunk 2: Streams 0 and 1, timeslot 1 Analog Trunk 3: Streams 0 and 1, timeslot 2 Analog Trunk 4: Streams 0 and 1, timeslot 3
Trunk signaling information	Analog Trunk 1: Streams 2 and 3, timeslot 0 Analog Trunk 2: Streams 2 and 3, timeslot 1 Analog Trunk 3: Streams 2 and 3, timeslot 2 Analog Trunk 4: Streams 2 and 3, timeslot 3
DSP voice information	Streams 4 and 5, timeslots 0..3
DSP signaling information	Streams 6 and 7, timeslots 0..3
Local telephone voice	Streams 8 and 9, timeslot 0
Local telephone signaling	Streams 10 and 11, timeslot 0
Audio interface	Streams 12 and 13, timeslot 0

6.3 QX 2000/80-4L MVIP-95 Switch Model

Figure 20 shows the QX 2000 MVIP-95 switch model. The specific use of each stream is as follows: MVIP Bus Streams MVIP bus Streams 0..15, timeslots 0..31 Local Bus Streams Trunk voice information Analog Trunk 1: Streams 0 and 1, timeslot 0 Analog Trunk 2: Streams 0 and 1, timeslot 1 Analog Trunk 3: Streams 0 and 1, timeslot 2 Analog Trunk 4: Streams 0 and 1, timeslot 3 Trunk signaling information Analog Trunk 1: Streams 2 and 3, timeslot 0 Analog Trunk 2: Streams 2 and 3, timeslot 1 Analog Trunk 3: Streams 2 and 3, timeslot 2 Analog Trunk 4: Streams 2 and 3, timeslot 3 DSP voice information Streams 4 and 5, timeslots 0..3 DSP signaling information Streams 6 and 7, timeslots 0..3 Local telephone voice Streams 8 and 9, timeslot 0 Local telephone signaling Streams 10 and 11, timeslot 0 Audio interface Streams 12 and 13, timeslot 0 Figure 20. QX 2000/80-4L Board MVIP-95 Switch Model

MVIP Bus Streams
MVIP bus	Streams 0..15, timeslots 0..31

Local Bus Streams
Trunk voice information	Analog Trunk 1: Streams 0 and 1, timeslot 0 Analog Trunk 2: Streams 0 and 1, timeslot 1 Analog Trunk 3: Streams 0 and 1, timeslot 2 Analog Trunk 4: Streams 0 and 1, timeslot 3
Trunk signaling information	Analog Trunk 1: Streams 2 and 3, timeslot 0 Analog Trunk 2: Streams 2 and 3, timeslot 1 Analog Trunk 3: Streams 2 and 3, timeslot 2 Analog Trunk 4: Streams 2 and 3, timeslot 3
DSP voice information	Streams 4 and 5, timeslots 0..3
DSP signaling information	Streams 6 and 7, timeslots 0..3
Local telephone voice	Streams 8 and 9, timeslot 0
Local telephone signaling	Streams 10 and 11, timeslot 0
Audio interface	Streams 12 and 13, timeslot 0

6.4 QX 2000/80-4L MVIP-90 Switch Model

Figure 21 shows the QX 2000 MVIP-90 switch model. The specific use of each stream is as follows: MVIP-90 Streams MVIP bus Streams 0..15, timeslots 0..31 Trunk voice information Analog Trunk 1: Stream 16, timeslot 0 Analog Trunk 2: Stream 16, timeslot 1 Analog Trunk 3: Stream 16, timeslot 2 Analog Trunk 4: Stream 16, timeslot 3 Trunk signaling information Analog Trunk 1: Stream 17, timeslot 0 Analog Trunk 2: Stream 17, timeslot 1 Analog Trunk 3: Stream 17, timeslot 2 Analog Trunk 4: Stream 17, timeslot 3 DSP voice information Stream 18, timeslots 0..3 DSP signaling information Stream 19, timeslots 0..3 Local telephone voice Stream 20, timeslot 0 Local telephone signaling Stream 21, timeslot 0 Audio interface Stream 22, timeslot 0 Figure 21. QX 2000/80-4L Board MVIP-90 Switch Model

MVIP-90 Streams
MVIP bus	Streams 0..15, timeslots 0..31
Trunk voice information	Analog Trunk 1: Stream 16, timeslot 0 Analog Trunk 2: Stream 16, timeslot 1 Analog Trunk 3: Stream 16, timeslot 2 Analog Trunk 4: Stream 16, timeslot 3
Trunk signaling information	Analog Trunk 1: Stream 17, timeslot 0 Analog Trunk 2: Stream 17, timeslot 1 Analog Trunk 3: Stream 17, timeslot 2 Analog Trunk 4: Stream 17, timeslot 3
DSP voice information	Stream 18, timeslots 0..3
DSP signaling information	Stream 19, timeslots 0..3
Local telephone voice	Stream 20, timeslot 0
Local telephone signaling	Stream 21, timeslot 0
Audio interface	Stream 22, timeslot 0

6.5 Default MVIP Switch Connections

When the board is booted, the following default connections are automatically made to connect the four line interfaces to the on-board DSP resources: Switch Connection MVIP-95 MVIP-90 Full duplex connection between line interface voice information and DSP resources. local:0:0..3 => local:5:0..3 local:4:0..3 => local:1:0..3 16:0..3 => 18:0..3 18:0..3 => 16:0..3 Simplex connection between DSP resources and line interface signaling information. local:6:0..3 => local:3:0..3 19:0..3 => 17:0..3
You can change the default routing, so that the board can interoperate with other boards connected to it over the MVIP bus. For more information about switching, refer to the Switching Service Developer's Reference Manual.

Switch Connection	MVIP-95	MVIP-90
Full duplex connection between line interface voice information and DSP resources.	local:0:0..3 => local:5:0..3 local:4:0..3 => local:1:0..3	16:0..3 => 18:0..3 18:0..3 => 16:0..3
Simplex connection between DSP resources and line interface signaling information.	local:6:0..3 => local:3:0..3	19:0..3 => 17:0..3

6.6 Mapping MVIP-95 to MVIP-90

The following diagram shows how streams are mapped in the MVIP-95 and MVIP-90 switching models: Figure 22. MVIP-90 and MVIP-95 Stream Mapping

6.7 FMIC Switching Restrictions

The MVIP-90 Switching standard is designed to use full duplex streams. When making a full duplex connection using stream 0, the timeslot on DSo0 is used to receive input, and output is driven onto the same timeslot on DSi0. For example:

MakeConnection ( 0:3 to 2:6 ) /* connects DSo0:3 to DSi2:6 */ MakeConnection ( 2:6 to 0:3 ) /* connects DSo2:6 to DSi0:3 */
The FMIC chip was designed to implement MVIP-90 switching. It has a "direction" bit in its connection memory for each timeslot, which selects either of the following modes: Send output to a timeslot on a DSi stream and receive input from the same timeslot on the corresponding DSo; or Receive input from a timeslot on a DSi and send output to the same timeslot on the corresponding DSo.
The FMIC cannot simultaneously send output to both DSi and DSo on the same timeslot on the same-numbered stream. It also cannot simultaneously receive input from DSi and DSo on the same timeslot.
For example, the following simplex connection is made: MakeConnection ( 0:3 to 2:6 ) /* connects DSo0:3 to DSi2:6 */
The FMIC establishes DSo0:3 as an input timeslot and DSi0:3 as an output timeslot. Even though there are no switch connections made to DSi0:3, the switch block cannot receive input from DSi0:3 because the direction is set in the FMIC by the switch command for DSo0:3.
When using the MVIP-95 switch model, a full duplex connection is: MakeConnection ( 0:3 to 5:6 ) /* connects DSo0:3 to DSi2:6 */ MakeConnection ( 4:6 to 1:3 ) /* connects DSo2:6 to DSi0:3 */
When a connection is made using stream 0 timeslot 3, the direction is set for timeslot 3 on stream 1. Stream 0 corresponds to DSo0, and stream 1 corresponds to DSi0 (see Figure 22).
In most applications, this switch blocking is completely invisible. However, for any board with an FMIC switch, you cannot connect the local DSP resources to the local network interfaces over the MVIP bus. Those connections must be made using the local streams. Likewise, you cannot connect two trunk channels on the same board over the MVIP bus.
Making a connection of any type involving a timeslot on an MVIP stream establishes the direction for that timeslot pair. The direction may not be changed until all connections involving the timeslot have been broken.
If you make arbitrary simplex connections, you may encounter blocking from an unavailable connection, where the direction bit on the connection has already been set in the opposite direction. Note: There is no direction associated with local streams.

6.8 MVIP-90/H Bus Interoperability

The QX 2000/100-4L board connects to the H.100 telephony bus. MVIP-90 and H-MVIP boards connect to the MVIP-90 bus.
The MVIP Bus Adapter is an adapter which connects the H.100 bus to the MVIP-90 bus located in the same computer chassis, as shown in Figure 23: Figure 23. H.100 Bus Interoperability with MVIP-90 Bus
The MVIP Bus Adapter allows boards connected to the H.100 bus to access the MVIP-90 bus, and allows MVIP-90 boards to access the first 16 streams of the H.100 bus. When connecting H.100 boards to the adapter, configure the first 16 H.100 streams in MVIP-90 mode.
The H.100 streams running in MVIP-90 mode are clocked at 2 MHz. Each stream has 32 timeslots. By default, the QX 2000/100-4L is configured for MVIP-90 compatibility mode with the first 16 streams configured for 2 MHz. Figure 24. MVIP Bus Adapter Streams

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