- J -

J1, J2, J3, J4, J5

Connector positions on the CompactPCI AG Quad board. The connectors are numbered sequentially from bottom to top, with J1 assigned to the lowest connector. As specified in PICMG 2.5, R1.0, the following connector assignments are used by the CompactPCI AG Quad board:

• J1 - 32-bit PCI bus.
• J2 - Not used, but defined as the expansion jack for 64-bit CompactPCI to accommodate the upper-32 bits and corresponding control signals.
• J3 - Not used.
• J4 - H.110 bus.
• J5 - Telephony I/O; when using a rear I/O configuration, the telephony signals are passed via this connector.
  See also CompactPCI, PICMG.

jitter

A lack of synchronization caused by varying transmission delays over a given connection.

jitter buffer

A mechanism for receiving data over a connection with jitter and manipulating the data into a synchronous stream of data without jitter. A jitter buffer can be implemented in many ways. A simple jitter buffer can be implemented as a fixed block of allocated memory. To implement a more robust, flexible version, create a linked list of data blocks dynamically, as needed, which provides a jitter buffer of virtually unlimited size.