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5.3 MC1 Clocking

The clocks in a multi-chassis system must all be synchronized. This means that all MVIP boards in the system must be driven by the same clock source. This section describes the MVIP bus and MC1 bus clock signals and how they interact.

5.3.1 MVIP Bus Clock Signals

The MVIP bus has two groups of clock signal lines: MVIP clocks SEC8K clock
Generally, all MVIP boards in a chassis receive clock from the MVIP clock lines. The SEC8K clock, if used at all, is usually a backup to the MVIP clocks. The SEC8K clock can be configured to be driven by a clock signal from the public switched telephone network via a digital network card (e.g. AG-T1).
In an MVIP system, one board must drive the MVIP bus clocks and all other boards connected to the MVIP bus must reference their clocks from the MVIP bus. The board that drives the MVIP bus clocks are called the MVIP clock master; all other boards are the MVIP clock slaves. The MC1 interface board is typically the MVIP clock master. This means all other MVIP boards in the same chassis are typically configured as MVIP slaves.
Figure 5. MVIP Bus Clock Configuration

5.3.2 MC1 Clock Signals

There are three independent clock signals on the MC1 bus: MC1_8K left clock signals right clock signals

The MC1_8K clock signal provides the source clock signal ultimately used by all the MC1 boards. In the Go-MVIP: MC1 Multi-Chassis MVIP Standard, the MC1_8K clock signal is called 8KREF. Either the left or right clock signal is configured to propagate this source clock signal to the MC1 bus. This clock line is used to control the timing in the system. The unused signal line may be configured as a backup clock signal.
The configuration of the clock lines is done using the mc1mon utility provided in the development kit or using the MC1 SwitchPath command MC1_CONFIG_CLOCK.
Figure 6. MC1 Bus Clock Signals
Each MC1 interface board in the system is configured in one of the following clock modes: primary master secondary master slave
The primary master synchronizes to the MC1_8K clock signal and generates either the left or right MC1 clocks. An MC1 system must have one and only one MC1 board configured as the primary master. This board will control the timing in the system.
As shown in Figure 7, the MC1 board is configured as the primary master driving the left clocks.
Figure 7. MC1 Primary Master
The secondary master is a backup to the primary master. It drives the clock that the primary master is not driving, using its own internal oscillator as a reference. In the event of a primary clock failure, the secondary master supplies all the necessary clocking signals. An MC1 system can have one and only one MC1 interface board selected as secondary master. The secondary master is optional.
As shown in Figure 8, the MC1 board is configured as the secondary master driving the right clock line.
Figure 8. MC1 Secondary Master
All remaining MC1 boards in the system must be configured in slave mode. The slave boards monitor the designated primary master. In the event of a primary clock failure, the slave cards can be configured to automatically fall back to the secondary master for their clocking requirements.
Figure 9. MC1 Slave
Figure 10 shows a typical MC1 system. MC1 board 1 is configured as the primary master synchronizing to the MC1_8K clock and driving the left clock signals. MC1 board 2 receives the left clock signals. It is also configured as the secondary master driving the right clock signals. MC1 board 3 is configured as a slave and receives its clock signal from the left clocks driven by the primary master.
Figure 10. MC1 Bus Clocking Configuration

5.3.3 MC1 Bus and MVIP Bus Clock Interaction

The clocks in a multi-chassis system must all be synchronized. As shown in Figure 11, a single digital network interface board is chosen as the overall system timing reference. This network board is configured to extract the 8 kHz telephone company reference and propagate it to the MVIP bus SEC8K signal. The MC1 board in that chassis is configured to propagate the SEC8K signal to the MC1_8K signal on the MC1 bus for use by the primary master. The MC1 primary master references the MC1_8K signal and drives the left or right clocks. All other MC1 boards will receive their clock from the left or right clock signals. Each MC1 board will drive the MVIP bus clocks in its PC chassis. Figure 11. MC1 Clock Propagation
Figure 12 shows an example MC1 system. In this example system: In PC #1, the network interface board receives the clock signal from the public switched telephone network and drives the SEC8K line on the MVIP bus. The MC1 board in PC #1 is configured to propagate the SEC8K clock signal to the MC1_8K clock on the MC1 bus. In PC #2, the MC1 board is configured to be the primary master. It references the MC1_8K clock and drives the left clocks on the MC1 bus. In PC #3, the MC1 board is configured as secondary master. It receives clocking from the left clocks and drives the right clocks. In PC #1, the MC1 board is configured as a slave receiving the clock from the left clocks. In each PC chassis, the MC1 board is configured as MVIP clock master driving the MVIP clock signals. All other boards in each chassis are configured as MVIP clock slaves.
In this manner, all boards in the multi-chassis system are ultimately synchronized to the same clock reference.

Figure 12. MC1 and MVIP Bus Interaction

5.3.4 Primary MVIP Clock Mode

Any MC1 board in the system can be configured to propagate the clock signal from the SEC8K line to the MC1_8K line. The MC1_8K line is then used as a reference to drive the left or right clocks.
In Primary MVIP mode, the MC1 board uses the MVIP clock as a reference to drive the left or right clocks. This configuration would be used if it is not possible to get a jitter-free SEC8K clock. In this mode, another board would be MVIP clock master.
Figure 13. Primary MVIP Mode

5.3.5 Clocking Configuration Summary

Each MC1 board has the following clocking parameters to configure: Clock Mode: Primary, Secondary, or Slave Clock Selection: Left or Right MVIP Clock Master Clock Source: MC1_8K or MVIP SEC8K and MC1_8K Interaction
To configure a typical MC1 system clocking: Configure a digital network card to drive SEC8K clock line. Configure the MC1 board in that chassis to transmit the clock from SEC8K to MC1_8K. Configure a primary master to drive the left or right clock line. If desired, configure a secondary master to drive the backup line. Configure MC1 boards to drive their local MVIP clocks. Configure slaves for autofallback.
The MC1 configuration is done using the mc1mon utility provided in the development kit or using the MC1 SwitchPath commands MC1_CONFIG and MC1_CONFIG_CLOCK.

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