5.1 Introduction 40

5.2 MC1 Switch Model 40

5.2.1 MVIP-90 Switch Model

5.2.2 MVIP-95 Switch Model

5.3 MC1 Switch Blocking 43

5.4 MC1 Clocking 44

5.4.1 MVIP Bus Clock Signals

5.4.2 MC1 Bus Clock Signals

5.4.3 MC1 Bus and MVIP Bus Clock Interaction

5.4.4 Primary MVIP Mode

5.4.5 Clocking Configuration Summary

5.5 Handling Faults 54

5.5.1 Recovering from Clocking Failures

5.5.2 Network Synchronization Failures

5.6 Indicator Lights (LEDs) 56

5.7 Removing an MC1 Board 57

5.1 Introduction

The MC1 board switches data between the MVIP-90 bus and the MC1 bus which allows MVIP boards in one PC to communicate with MVIP boards in another PC. The PCs are connected by external cables that provide the physical connection of the MC1 bus. Each PC in the system must have a Natural MicroSystems MC1 board.

This chapter presents information about the MC1 board and about building a multi-chassis system including:

• MC1 switch models

• MC1 clocking

• Handling MC1 faults

• Setting up a multi-chassis system

The MC1 interface board contains two MVIP enhanced compliant switches which allow an application to make connections between the MVIP-90 bus and the MC1 bus. The MC1 board has access to all 16 streams, with 32 timeslots each, of the MVIP-90 bus.

On each MC1 board, there are 22 streams, with 64 timeslots each, associated with the MC1 bus. All of the MC1 streams may be used to receive data (input ports). 256 simultaneous connections can be made from any of the MC1 input ports. Each MC1 board in the system can monitor all data on the MC1 bus.

Each MC1 board can drive up to four of the MC1 streams (output ports). Only one MC1 board at a time may drive an MC1 stream. If an MC1 board drives an MC1 stream, it drives all of the timeslots on that stream.

The configuration of the MC1 output streams can be done using the mc1mon utility provided in the development kit or using the MC1 driver command MC1_CONFIG.

The MVIP streams and MC1 streams may be addressed using the MVIP-90 switch model (via SwitchPath) or the MVIP-95 switch model (via CT Access).

The MVIP-90 switch model is shown in Figure 7. The MVIP-90 bus streams are addressed by the application as streams 0..15. MC1 streams are addressed as streams 16..37.

The MC1 output streams are grouped into logical streams A, B, C, and D, as shown in Figure 7. When configuring the four MC1 streams driven by a particular MC1 board, at most one stream from each of the logical groups can be chosen:

· Group A	16, 20, 24, 28, 32, 36
· Group B	17, 21, 25, 29, 33, 37
· Group C	18, 22, 26, 30, 34
· Group D	19, 23, 27, 31, 35

For example, you may select to drive streams 16, 17, 18, 19 or 20, 33, 26, 35 with a single MC1 interface board. Streams 16, 20, 30, 31 could not be chosen since streams 16 and 20 are both from logical group A.

The MC1 streams are referred to by stream numbers 16 through 37 in switching commands, not by groups A,B,C, or D. The choice of streams driven by an MC1 board can be dynamically changed.

Figure 7. MC1 Board - MVIP-90 Switch Model

The MVIP-95 switch model is shown in Figure 8. The MVIP-90 bus streams are addressed by the application as MVIP bus: streams 0..15. The MC1 streams are addressed as MC1 Bus:streams 0..43.

The MC1 output streams are group into logical streams A, B, C, and D as shown in Figure 8. When configuring the four MC1 streams driven by a particular MC1 board, only one stream from each of the logical groups can be chosen:

· Group A	1,9,17,25,33,41
· Group B	3,11,19,27,35,43
· Group C	5,13,21,29,37
· Group D	7,15,23,31,39

For example, you may select to drive streams 1, 3, 5, 7 or 9, 35, 21, 39 with a single MC1 interface board. Streams 1, 9, 29, 31 could not be chosen since streams 1 and 9 are both from logical group A.

The MC1 streams are referred to by stream numbers 0 through 43 in switching commands, not by groups A,B,C, or D. The choice of streams driven by an MC1 board can be dynamically changed.

Figure 8. MC1 Board - MVIP-95 Switch Model

MC1 switching is implemented using two FMIC (Flexible MVIP Integrated Circuit) chips.

Each FMIC chip has a direction bit in its connection memory for each timeslot in an MVIP stream pair (DSo and DSi), which designates the timeslot in both streams as either an input or an output of the switch block.

By making a switch connection involving a timeslot on an MVIP stream, the timeslot is configured as an input or an output. The direction may not be changed until the connection involving the timeslot has been broken.

Since the direction bit specifies a stream pair, configuring a timeslot on DSo0 (for MVIP-90, MVIP Bus: Stream 0 for MVIP-95) as an input stream automatically configures the same timeslot on DSi0 (for MVIP-90, MVIP Bus: Stream 1 for MVIP-95) as an output stream.

The following simultaneous connections would not be allowed on a board with a single FMIC:

MVIP-90 Commands	MVIP-95 Commands
MakeConnection(0:0 to 16:0) MakeConnection(8:0 to 17:0)	MakeConnection(MVIP:0:0 to LOCAL:1:0) MakeConnection(MVIP:1:0 to LOCAL:3:0)

FMIC blocking is different on the MC1 board because MC1 switch connections are distributed between the two FMIC chips. If the two switch connections specified in the previous table are made, one switch connection could be made on the first FMIC and the second connection could then be made on the second FMIC.

Each FMIC supports 128 switch connections. If the first FMIC has 128 switch connections, and the two switch connections specified in the previous example were then attempted, the second connection would return an error. The first FMIC cannot be used for any more connections and the second FMIC cannot make both of the connections because of the FMIC "direction" bit restriction.

Note: This does not apply to MC1 local streams.

The clocks in a multi-chassis system must all be synchronized. This means that all MVIP boards in the system must be driven by the same clock source. This section describes the MVIP bus and MC1 bus clock signals, and how they interact.

The MVIP bus has two groups of clock signal lines:

• MVIP clocks

• SEC8K clock

Generally, all MVIP boards in a PC chassis receive clock from the MVIP clock lines. The SEC8K clock, if used at all, is usually a backup to the MVIP clocks. The SEC8K clock can be configured to be driven by a clock signal from the public switched telephone network via a digital network board (e.g. AG-T1).

In an MVIP system, one board must drive the MVIP bus clocks. All other boards connected to the MVIP bus must reference their clocks from the MVIP bus. The board that drives the MVIP bus clocks is called the MVIP clock master; all other boards are MVIP clock slaves. The MC1 interface board is typically the MVIP clock master. This means all other MVIP boards in the same chassis are typically configured as MVIP clock slaves.

MC1 boards are configured as clock masters or clock slaves using the MC1 driver command MC1_CONFIG_CLOCK, or using the CT Access command swiConfigBoardClock.

Figure 9. MVIP Bus Clock Configuration

There are three independent clock signals on the MC1 bus:

• MC1_8K (also called 8KREF)

• left clock signals

• right clock signals

The MC1_8K clock signal provides the source clock signal ultimately used by all the MC1 boards. In the Go-MVIP: MC1 Multi-Chassis MVIP Standard, the MC1_8K clock signal is called 8KREF. Either the left or right clock signal is configured to propagate this source clock signal to the MC1 bus. This clock line is used to control the timing in the MC1 system. The unused signal line may be configured as a backup clock signal.

The configuration of the clock lines is done using the mc1mon utility, using the MC1 driver command MC1_CONFIG_CLOCK, or using the CT Access switching commands.

Each MC1 interface board in the system is configured in one of the following clock modes:

• primary master

• secondary master

• slave

The primary master synchronizes to the MC1_8K (8KREF) clock signal and generates either the left or right MC1 clocks. An MC1 system must have one and only one MC1 board configured as the primary master. This board will control the timing in the MC1 system.

In the example shown in Figure 10, the MC1 board is configured as the primary master driving the left clocks.

Figure 10. MC1 Primary Master

The secondary master is a backup to the primary master. It drives the clock that the primary master is not driving, using its own internal oscillator as a reference. In the event of a primary clock failure, the secondary master supplies all the necessary clocking signals. An MC1 system can have only one MC1 board selected as secondary master. The secondary master is optional.

In the example shown in Figure 11, the MC1 board is configured as the secondary master driving the right clock line.

Figure 11. MC1 Secondary Master

All remaining MC1 boards in the system must be configured in slave mode. The slave boards monitor the clock lines driven by the designated primary master. In the event of a primary clock failure, the slave boards can be configured to automatically fall back to the secondary master for their clocking requirements.

Figure 12. MC1 Slave

Figure 13 shows a typical MC1 system. MC1 board 1 is configured as the primary master synchronizing to the MC1_8K (8KREF) clock and driving the left clock signals. MC1 board 2 receives the left clock signals. It is configured as the secondary master, driving the right clock signals. MC1 board 3 is configured as a MC1 slave, and receives its clock signal from the left clocks driven by the primary master.

Figure 13. MC1 Bus Clocking Configuration

The clocks in a multi-chassis system must all be synchronized. As shown in Figure 14, a single digital network interface board (e.g., AG-T1) is chosen as the overall system timing reference. This network board is configured to extract the 8 kHz telephone company reference and propagate it to the MVIP bus SEC8K signal.

The MC1 board in that chassis is configured to propagate the SEC8K signal to the MC1_8K (8KREF) signal on the MC1 bus for use by the primary master. The MC1 primary master references the MC1_8K (8KREF) signal and drives the left or right clocks.

All other MC1 boards receive their clock from the left or right clock signals. Each MC1 board typically drives the MVIP bus clocks in its PC chassis.

Note: While any MC1 board in the system can be configured to propagate the clock signal from the SEC8K line to the MC1_8K (8KREF) line, it is recommended that the primary master propagate the SEC8K signal.

Figure 14. MC1 Clock Signal Propagation

Note: It is recommended that the SEC8K clock line for each MVIP bus be driven by a digital network board in its chassis for use as a backup timing reference.

Figure 15 shows an example MC1 system:

• In PC #1, the network interface board receives the clock signal from the public switched telephone network and drives the SEC8K line on the MVIP bus.

• The MC1 board in PC #1 is configured to propagate the SEC8K clock signal to the MC1_8K (8KREF) clock on the MC1 bus.

• In PC #1, the MC1 board is configured to be the MC1 primary master. It references the MC1_8K (8KREF) clock and drives the left clocks on the MC1 bus.

• In PC #3, the MC1 board is configured as secondary master. It receives clock signals from the left clocks and drives the right clocks.

• In PC #2, the MC1 board is configured as a clock slave receiving the clock from the left clocks.

• In each PC chassis, the MC1 board is configured as MVIP clock master and it drives the MVIP clock signals.

• All other boards in each chassis are configured as MVIP clock slaves.

In this manner, all boards in the multi-chassis system are ultimately synchronized to the same clock reference.

Figure 15. MC1 and MVIP Bus Interaction

Note: While any MC1 board in the system can be configured to propagate the clock signal from the SEC8K line to the MC1_8K (8KREF) line, it is recommended that the primary master propagate the SEC8K signal.

An additional configuration for the MC1 primary master is to configure the MC1 board in Primary MVIP mode.

In Primary MVIP mode, the primary master MC1 board is configured to use the MVIP bus clock as a reference to drive the left or right clocks. This configuration would be used if it is not possible to get a jitter-free SEC8K clock to drive the MC1_8K (8KREF) line.

If the MC1 board is configured in Primary MVIP mode, another MVIP board in the chassis must be configured as the MVIP clock master. In standard configurations, the MC1 board in each chassis is configured as the MVIP bus clock master.

Figure 16. Primary MVIP Mode

Each MC1 board has the following clocking parameters to configure:

• Clock Mode: Primary, Secondary, or Slave

• Clock Selection: Left or Right

• MVIP Clock Master

• SEC8K and MC1_8K (8KREF) Interaction

To configure clocking for a typical MC1 system:

1. Configure a digital network card to drive SEC8K clock.

2. Configure the MC1 board in that chassis to transmit the clock from SEC8K to MC1_8K (8KREF).

3. Configure a primary master to drive the left or right clock signals.

4. If desired, configure a secondary master to drive the backup clock.

5. Configure MC1 boards to drive their local MVIP clocks.

6. Configure slaves for autofallback.

The MC1 configuration is done using the mc1mon utility, using the MC1 driver commands MC1_CONFIG and MC1_CONFIG_CLOCK, or using CT Access switching commands.

The MC1 board is equipped with a watchdog timer. The watchdog timer is used to determine if system software hangs up during normal operation. When enabled, the watchdog timer must be periodically refreshed by the application, or it will electronically disconnect the MC1 board from the MC1 bus. The MC1 board will no longer transmit data or clock signals.

The watchdog timer is refreshed by reading the status of the MC1 board (driver command MC1_QUERY_STATUS). If the status of the MC1 board is not read by the time the watchdog timer has fired (approximately 9 seconds), the MC1 card will electrically disconnect itself from the MC1 bus.

If a clocking failure is detected on the primary MC1 clock line, the autofallback feature will cause a slave to switch from referencing the primary master clock line to start referencing the backup clock line.The autofallback applies to slaves only. If a secondary master detects a clocking failure, it reverts to using its internal clock.

You enable the watchdog timer and autofallback feature with the MC1_CONFIG driver command.

An application should periodically call the MC1_QUERY_STATUS driver command to determine when a loss of clock source is detected by the MC1 board and take action to recover.

When the MC1 board configured as primary master fails, and the watchdog timer is enabled, an alarm is noted. The MC1 board is automatically disconnected from driving the MC1 bus. The secondary master reverts to using its internal clock to drive the backup clock signal. If autofallback is enabled, the slaves automatically switch to reference the backup clock driven by the secondary master. The application should be checking for a failure condition by regularly invoking the MC1 command MC1_QUERY_STATUS.

When a primary master clock failure is detected, the application should do the following:

1. Demote the primary master board to a slave (if it is still functioning).

2. Promote the secondary master board or a slave board to be primary master.

3. Promote a slave board to be secondary master (if desired).

4. Reconfigure the new secondary master board (if there is one) and all slaves to reference the clock driven by the new primary master board.

5. Power down and remove the failed MC1 board from the multi-chassis system by removing the MC1 cable.

When a secondary master clock failure is detected, the application should do the following:

1. Demote secondary master board to a slave (if possible).

2. Promote a slave board to secondary master.

If the network board which is driving the SEC8K clock signal reports a loss of synchronization with the PSTN, choose an alternate network board as the source of synchronization.

If the alternate board is in the same chassis as the original network board:

1. Configure the original network card to stop driving SEC8K.

2. Configure the alternate network board to start driving SEC8K.

If the alternate network board is in a different chassis:

1. Configure the original network board to stop driving SEC8K.

2. Configure the MC1 board in the chassis with the original network board to stop propagating SEC8K to MC1_8K (8KREF).

3. Configure the alternate network board to start driving SEC8K.

4. Configure an MC1 board in the chassis with the alternate network board to propagate SEC8K to MC1_8K (8KREF).

There are three LEDs on the MC1 interface board. They are colored red, yellow, and green.

The red LED indicates if the board has detected a clocking error. The error can be one or more of the following:

• invalid input clock source

• watchdog timeout (see Section 5.5, Handling Faults)
  Note: Once an error has been detected, the red LED will remain lit until the error has been cleared and the MC1 board is reconfigured with the MC1_CONFIG_CLOCK driver command or with the mc1mon utility.

The yellow LED indicates if the MC1 board is driving one of the MC1 clocks. If the yellow LED is illuminated, the board is driving either the right or left MC1 clock. This means it is either a primary or secondary master. If the yellow LED is off, the board is a clock slave.

The green LED indicates which MC1 clock is being used. If the green LED is on, the right clock is being used. If the green LED is off, then the left clock is being used.

The following table summarizes the valid LED combinations:

Red	Yellow	Green	Description
ON	--	--	Board has detected an error
OFF	OFF	OFF	Board is configured as a slave using the left clocks
OFF	OFF	ON	Board is configured as a slave using the right clocks
OFF	ON	OFF	Board is a primary or secondary master driving the left clocks
OFF	ON	ON	Board is a primary or secondary master driving the right clocks

Only powered-down MC1 slave boards can be removed from the system without causing clocking errors. The proper method of removing a primary master board is to demote it to slave status. This causes the other MC1 boards in the system to switch to the secondary master's clock if autofallback is configured. You can then power down the old primary master board and remove the MC1 bus connector. The secondary master board should be promoted to primary master and a slave promoted as a new secondary master as defined in Section 5.5.1.