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When the trunk transmission reaches the AG-T1 or AG-E1 board, the board places the voice and signaling information directly in timeslots in MVIP streams. The actual streams used depend upon:
If DigitalMode=CAS (its default setting), information is routed to accommodate a T1 channel-associated signaling configuration, where:
On the MVIP bus, this information is presented as follows (see Figure 24):
Figure 24: Connecting T1 Timeslots To MVIP Timeslots (DigitalMode=CAS)
If DigitalMode=PRI, signaling information is routed differently to accommodate the T1 ISDN common channel signaling configuration, where:
The AG-T1 routes this information as follows (see Figure 25):
Figure 25: Connecting T1 Timeslots to MVIP Timeslots (DigitalMode=PRI)
If DigitalMode is set to RAW, information is routed to accommodate a Network Facility Associated Signaling (NFAS) configuration, where no D channel is present on the T1 trunk (see section 5.3.2):
The AG-T1 routes this information as follows (see Figure 26):
Figure 26: Connecting T1 Timeslots To MVIP Timeslots (DigitalMode=RAW)
With AG-E1s, DigitalMode only affects how signaling information is routed. Regardless of the DigitalMode setting, the AG-E1 routes the voice information as follows:
Figure 27 illustrates how voice channel data is assigned to MVIP timeslots:
Figure 27: Connecting E1 B Channels To MVIP Timeslots (All Modes)
If DigitalMode=CAS (its default setting), signaling information is routed to accommodate an E1 channel-associated signaling configuration, where E1 channel 16 carries signaling information for all other channels. The signaling information in E1 timeslot 16 for each channel is broken out and placed in a corresponding timeslot on MVIP-95 LOCAL,2 and LOCAL,3 (MVIP-90 stream 17). For example, the voice information for E1 timeslot 7 appears in MVIP-95 LOCAL,0,6 and LOCAL,1,6 (MVIP-90 stream:timeslot 16:6). The signaling information for E1 timeslot 7 appears in MVIP-95 LOCAL,2,6 and LOCAL,3,6 (MVIP-90 stream:timeslot 17:6).
Figure 28 illustrates how signaling data is distributed:
Figure 28: Breaking Out Signaling Information From E1 Stream 16 (CAS Mode)
Thus, to CT Access or AG Access, there is a single set of streams carrying voice and signaling information to and from the E1 trunk, where each timeslot contains the voice or signaling information for one E1 channel.
If DigitalMode=PRI, signaling information is routed differently to accommodate an ISDN common channel signaling configuration, where CCS signaling packets are transmitted in channel 16 instead of CAS bits. All signaling information from channel 16 is routed to MVIP-95 LOCAL,8,0 and LOCAL,9,0 (MVIP-90 stream:timeslot 20:0) (See Figure 29.) This stream connects to the board's HDLC controller, which processes the D channel information from each frame.
Figure 29: Routing E1 Channel 16 Data To HDLC Controller (PRI Mode)
This section describes how the T1 or E1 trunk and processing resource streams fit in the context of the AG-T1 and AG-E1's MVIP switch model. (For more information about MVIP switch models, see Getting Started With MVIP Switching.)
Figure 30 shows the AG-T1 and AG-E1 switch model in MVIP-95 terms. The specific use of each MVIP stream is as follows:
Figure 30: AG-T1 and AG-E1 Switch Model (MVIP-95)
Figure 31 shows the AG-T1 and AG-E1 switch model in MVIP-90 terms. The specific use of each MVIP stream is as follows:
Figure 31: AG-T1 and AG-E1 MVIP Switch Model (MVIP-90)
If MVIP switching is disabled in your AG configuration file (EnableMvip=NO), certain default MVIP connections are made on AG-T1 and AG-E1 boards. The exact settings depend upon the setting of DigitalMode, as shown in the following table:
|
DigitalMode |
Default routing |
|
CAS |
These settings channel all information from the incoming voice and signaling streams to DSP processing resources. This allows the board to process the information, send or receive faxes, etc. |
|
PRI or RAW |
|
You may wish to change this default routing, so the board can interoperate with other boards connected to it via the MVIP bus. To do so, enable MVIP switching.
With MVIP switching enabled, there is no default routing. You can control the routing using any of the software tools described in section 1.3.3.
Note: If you use SwitchPath, note that the board's switch device name is as follows:
For introductory information about MVIP switching, see Getting Started With MVIP Switching.
The MVIP-90 Switching Standard is designed to use full duplex streams. When making a full duplex connection using stream 0, the timeslot on DSo0 is used to receive input, and output is driven onto the same timeslot on DSi0. For example:
MakeConnection ( 0:3 to 2:6 ) /* connects DSo0:3 to DSi2:6 */ MakeConnection ( 2:6 to 0:3 ) /* connects DSo2:3 to DSi0:6 */
The FMIC chip was built for implementing MVIP-90 switching. It has a direction bit in its connection memory for each timeslot, that selects either of the following modes:
The FMIC cannot simultaneously send output to both DSi and DSo on the same timeslot on the same-numbered stream, and also cannot simultaneously receive input from both DSi and DSo on the same timeslot.
For example, the following simplex connection is made:
MakeConnection ( 0:3 to 2:6 ) /* connects DSo0:3 to DSi2:6 */
The FMIC establishes DSo0:3 as an input timeslot and DSi0:3 as an output timeslot. Even though there are no switch connections made to DSi0:3, the switch block cannot receive input from DSi0:3 because the direction is set in the FMIC by the switch command for DSo0:3.
When using the MVIP-95 switch model, a full duplex connection is:
MakeConnection ( 0:3 to 5:6 ) /* connects DSo0:3 to DSi2:6 */ MakeConnection ( 4:6 to 1:3 ) /* connects DSo2:6 to DSi0:3 */
When a connection is made using stream 0 timeslot 3, the direction is set for timeslot 3 on stream 1. Stream 0 corresponds to DSo0, and stream 1 corresponds to DSi0 (see Figure 32).
In most applications, this switching restriction is completely invisible. However, for any board with an FMIC switch, you cannot connect the local DSP resources to the local network interfaces over the MVIP bus. Those connections must be made using the local streams. Likewise, you cannot connect two trunk channels on the same board over the MVIP bus.
Making a connection of any type involving a timeslot on an MVIP stream establishes the direction for that timeslot pair. The direction may not be changed until all connections involving the timeslot have been broken.
If you make arbitrary simplex connections, you may encounter blocking from an unavailable connection, where the direction bit on the connection has already been set in the opposite direction.
Note that there is no direction associated with local streams.
Figure 32: FMIC Connection Limitations
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