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DigitalMode depending upon whether your AG-T1 or AG-E1 will be using a channel-associated signaling protocol (CAS), an ISDN protocol, or an ISDN protocol with Network Facility Associated Signaling (NFAS). DigitalMode does the following:
LineCode setting.
DigitalMode can be set to any of the following:
CAS makes settings appropriate for channel-associated signaling.
PRI makes settings appropriate for primary-rate ISDN.
RAW makes settings appropriate for primary-rate ISDN with Network
Facility Associated Signaling (NFAS).
Board x section for each AG-T1 and AG-E1 board in your AG configuration file.
DigitalMode defaults to CAS.
D4 (AG-T1 only) Standard superframe formatting.
ESF (AG-T1 only) Extended superframe formatting.
CEPT (AG-E1 only) Framing format conforming to ITU recommendation
G.703 for PCM 30 (30 telephone channels with channel-associated
signaling).
Board x section for each AG-T1 and AG-E1 board in your AG configuration file.
D4 for AG-T1 boards, CEPT for AG-E1 boards
COMMON section of the AG configuration file.
Interrupt has no default.
LineCode (optional)
Board x section of each AG-T1 or
AMI_BELL if DigitalMode=CAS; otherwise B8ZS
AG-E1 boards: HDB3
LineLength (optional)
RunFile has no default value.
EnableMVIP keyword in your AG configuration file. The allowed values for EnableMVIP are:
|
Value
|
Definition
| |
NO
|
MVIP switching is disabled. When you set EnableMVIP this way (and run agmon to initialize the board), the trunk line is automatically linked to the board's DSPs, as described in Chapter 6. This provides the trunk channels with the necessary DSP resources. However, you cannot reroute the channels to other boards or other external resources.
| |
YES
|
MVIP switching is enabled. When you set EnableMVIP this way (and run agmon to initialize the board), no switch connections are automatically made. To control switching, you can use the CT Access Switching service.
| |
ClockRef statement for each board so it indicates whether the board will be the MVIP bus clock master or a slave. The allowed values for ClockRef are:
You may also wish to configure one board to drive the secondary 8 kHz bus clock (Sec8k clock). For details, see Appendix C.
in UNIX.
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