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Appendix B

Hardware Specifications

This appendix presents the mechanical specifications for the AG-24/30/48/60 boards, including ISA and MVIP bus connectors, and daughterboard mechanical requirements.


Feature	AG board	Specification
Board capacity	AG-24	24 ports, 7 MIPS per port
	AG-30	30 ports, 5.7 MIPS per port
	AG-48	48 ports, 8.3 MIPS per port
	AG-60	60 ports, 6.6 MIPS per port
TDM bus	AG-24/30/48/60	One complete MVIP-90 bus interface per board
DSP processing power	AG-24	6 DSPs
	AG-30	6 DSPs
	AG-48	14 DSPs, six on the baseboard and an additional eight DSPs on a daughterboard
	AG-60	14 DSPs, six on the baseboard and an additional eight DSPs on a daughterboard
Microprocessor	AG-24/30/48/60	Microprocessor: 25 MHz 80386SX
Memory	AG-24/30/48/60	4 MB of dedicated DRAM and 256 KB of fast static RAM for the on-board microprocessor (128 KB shared with the host and 128 KB shared with the DSPs)

Pinouts and signals of the MVIP bus follow specifications in the MVIP-90 Standard, Release 1.1 Manual.
The AG-24/30/48/60 boards do not have telephone network interface capability. Therefore, the MVIP bus clock signal must be driven by another MVIP board with appropriate MVIP clock generating circuitry.

Bicolor LEDs provide visual feedback of proper system operation. The LEDs are located as shown in Figure 7: Figure 7. LEDs on AG-24/30/48/60 Baseboard
D1, D2, D3, D4, D5, D6, and D7 show the arbiter request/grant status for each DSP.
D9 and D10 indicate the status of the host interface. D11 indicates the state of the DSP interface. LED Color Condition Meaning D9 Green ON SRAM "not busy" Green OFF SRAM is "busy" Red ON Coprocessor is reset Red OFF Coprocessor is unreset D10 Green ON Host owns SRAM Green OFF Coprocessor owns SRAM Red ON Coprocessor transmits to host Red OFF Host transmits to coprocessor D11 Green ON MVIP streams 0, 1, 4, and 5 are selected Green OFF MVIP streams 2, 3, 6, and 7 are selected Red ON DSP section is reset Red OFF DSP section is unreset

LED	Color	Condition	Meaning
`D9`	Green	ON	SRAM "not busy"
	Green	OFF	SRAM is "busy"
	Red	ON	Coprocessor is reset
	Red	OFF	Coprocessor is unreset
`D10`	Green	ON	Host owns SRAM
	Green	OFF	Coprocessor owns SRAM
	Red	ON	Coprocessor transmits to host
	Red	OFF	Host transmits to coprocessor
`D11`	Green	ON	MVIP streams 0, 1, 4, and 5 are selected
	Green	OFF	MVIP streams 2, 3, 6, and 7 are selected
	Red	ON	DSP section is reset
	Red	OFF	DSP section is unreset


Feature	Specification
PC interface	128 KB of static RAM
Electrical	PC/AT bus designed to IEEE P966 ISA
Mechanical	PC/AT form factor, designed to meet IBM's PC/AT Prototype Adapter Reference Manual #6361674 specifications
Bus speed	4 - 12 MHz
I/O addressing	Switch-select any of the 64 I/O base addresses
I/O mapped memory	28 KB on-board interface memory accessed at DMA rates via I/O string move
Interrupts	Choice of 7 software-configurable interrupt lines

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