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4.4 Multi-Chassis Clock Configuration

The clocks in a multi-chassis system must all be synchronized. This means that all boards in all chassis in the system must be driven by the same clock source.
There are three independent clock signals on the MC1 bus: MC1_8K (also called 8KREF) Left clock signals Right clock signals
In the Go-MVIP: MC1 Multi-Chassis MVIP Standard, the MC1_8K clock signal is called 8KREF. The MC1_8K (8KREF) clock signal provides the source clock signal ultimately used by all the MC1 boards. Either the left or right clock signal is configured to propagate this source clock signal to the MC1 bus. This clock line (left or right) is used to control the timing in the system. The unused signal line (left or right) may be configured as a backup clock signal.
Each MC1 board in the system is configured in one of the following clock modes: Primary master The primary master synchronizes to the MC1_8K (8KREF) clock signal and generates either the left or right MC1 clocks. An MC1 system must have one and only one MC1 board configured as the primary master. This board will control the timing in the system. Secondary master The secondary master is a backup to the primary master. It drives the clock that the primary master is not driving, synchronizing to the primary master. In the event of a primary clock failure, the secondary master supplies all the necessary clocking signals. An MC1 system can have one and only one MC1 interface board selected as secondary master. The secondary master is optional. Slave All remaining MC1 boards in the system must be configured in slave mode. The slave boards monitor the designated primary master. In the event of a primary clock failure, the slave boards can be configured to automatically fall back to the secondary master for their clocking requirements.
Figure 63 shows a typical MC1 system. MC1 board 1 is configured as the primary master synchronizing to the MC1_8K (8KREF) clock and driving the left clock signals. MC1 board 2 receives the left clock signals. It is also configured as the secondary master driving the right clock signals. MC1 board 3 is configured as a slave and receives its clock signal from the left clocks driven by the primary master.
Figure 63. MC1 Bus Clocking Configuration

4.4.1 MC1 Bus and MVIP Bus Clock Interaction

The clocks in a multi-chassis system must all be synchronized. As shown in Figure 64, a single digital network interface board (e.g., AG-T1) is chosen as the overall system timing reference. This network board is configured to extract the 8 KHz telephone company reference and propagate it to the MVIP bus SEC8K signal.
The MC1 board in that chassis is configured to propagate the SEC8K signal to the MC1_8K (8KREF) signal on the MC1 bus for use by the primary master. The MC1 primary master references the MC1_8K (8KREF) signal and drives the left or right clocks.
All other MC1 boards receive their clock from the left or right clock signals. Each MC1 board typically drives the MVIP bus clocks in its PC chassis. Note: While any MC1 board in the system can be configured to propagate the clock signal from the SEC8K line to the MC1_8K (8KREF) line, it is recommended that the primary master propagate the SEC8K signal. Figure 64. MC1 Clock Propagation Note: It is recommended that the SEC8K clock line for each MVIP bus be driven by a digital network board in its chassis for use as a backup timing reference.

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