(Page 1 of 1 in this chapter)

Appendix C

Switch Implementation

Introduction

In the MVIP-90, H-MVIP, and H.100 specifications there are no hardware limitations on how information is exchanged. Switch implementations may have built-in limitations, referred to as switch blocking.

HMIC Switch

The HMIC (H.100/MVIP Integrated Circuit) provides a complete interface to the H.100 bus. The HMIC interfaces to industry standard telephony buses by providing all the signals needed for the H.100, H-MVIP, and MVIP-90 buses.
The HMIC provides up to 128 full duplex connections to any of the 4096 timeslots on the H.100 bus.
Up to 16 local streams are available on the HMIC. Local bus to local bus switching provides up to 1024 connections.

HMIC Switching Restrictions

The number of H.100 connections are limited to a maximum of 128 full duplex or 256 simplex (or half duplex) connections, in any combination, from either: H.100 bus to the local bus, or H.100 bus to H.100 bus.

FMIC Switch

The FMIC (Flexible MVIP Interface Circuit) provides a complete enhanced-compliant interface to the MVIP-90 bus. The FMIC supports up to 128 full duplex connections to any of the 512 timeslots on the MVIP-90 bus.

FMIC Switching Restrictions

The MVIP-90 Switching Standard is designed to use full duplex streams. When making a full duplex connection using stream 0, the timeslot on DSo0 is used to receive input, and output is driven onto the same timeslot on DSi0. For example:

MakeConnection ( 0:3 to 2:6 ) /* connects DSo0:3 to DSi2:6 */ MakeConnection ( 2:6 to 0:3 ) /* connects DSo2:3 to DSi0:6 */
The FMIC chip was built for implementing MVIP-90 switching. It has a direction bit in its connection memory for each timeslot, that selects either of the following modes: Send output to a timeslot on a DSi stream and receive input from the same timeslot on the corresponding DSo; or Receive input from a timeslot on a DSi and send output to the same timeslot on the corresponding DSo.
The FMIC cannot simultaneously send output to both DSi and DSo on the same timeslot on the same-numbered stream, and also cannot simultaneously receive input from both DSi and DSo on the same timeslot.
For example, the following simplex connection is made: MakeConnection ( 0:3 to 2:6 ) /* connects DSo0:3 to DSi2:6 */
The FMIC establishes DSo0:3 as an input timeslot and DSi0:3 as an output timeslot. Even though there are no switch connections made to DSi0:3, the switch block cannot receive input from DSi0:3 because the direction is set in the FMIC by the switch command for DSo0:3.
When using the MVIP-95 switch model, a full duplex connection is: MakeConnection ( 0:3 to 5:6 ) /* connects DSo0:3 to DSi2:6 */ MakeConnection ( 4:6 to 1:3 ) /* connects DSo2:6 to DSi0:3 */
When a connection is made using stream 0 timeslot 3, the direction is set for timeslot 3 on stream 1. Stream 0 corresponds to DSo0, and stream 1 corresponds to DSi0 (see Figure 67).
In most applications, this switch blocking is completely invisible. However, for any board with an FMIC switch, you cannot connect the local DSP resources to the local network interfaces over the MVIP bus. Those connections must be made using the local streams. Likewise, you cannot connect two trunk channels on the same board over the MVIP bus.
Making a connection of any type involving a timeslot on an MVIP stream establishes the direction for that timeslot pair. The direction may not be changed until all connections involving the timeslot have been broken.
If you make arbitrary simplex connections, you may encounter blocking from an unavailable connection, where the direction bit on the connection has already been set in the opposite direction.
Note that there is no direction associated with local streams. Figure 67. MVIP-90 and MVIP-95 Stream Mapping

Digital Crosspoint Switches

A MVIP-90 standard-compliant interface can be implemented with four digital crosspoint switches.
Connections between local streams are not supported in a MVIP-90 standard-compliant switch. Local stream to local stream connections must be made over the MVIP bus.

(Page 1 of 1 in this chapter)

tech_support@nmss.com