(Page 1 of 1 in this chapter)

Chapter 4

MVIP Clocking

4.1 Introduction

: 4.1.1 Telephony Bus Signals

4.2 Single Chassis Clock Configuration

: 4.2.1 H.100 Clock Configuration
: 4.2.2 MVIP-90 and H-MVIP Clock Configuration

4.3 Bus Clocking Fallback Behavior

: 4.3.1 H.100 Bus Primary Reference Trunk Failure
: 4.3.2 MVIP-90 and H-MVIP Bus Primary Reference Trunk Failure

4.4 Multi-Chassis Clock Configuration

: 4.4.1 MC1 Bus and MVIP Bus Clock Interaction

4.1 Introduction

In a single board MVIP system, you do not have to be concerned with clock configuration. Clock configuration is required in applications involving multiple telephony boards or multi-chassis systems.

4.1.1 Telephony Bus Signals

The following table details the clock signals on the different telephony buses. MVIP-90 Bus · Data Streams 16 streams labeled DSi0..7 and DSo0..7 · Clock Signals Bit clocks and framing signals Backup timing reference (SEC8K) H-MVIP Bus · Data Streams 24 streams labeled HDS0..23 · Clock Signals Bit clocks and framing signals Secondary timing reference (SEC8K) Compatibility clocks (to operate in MVIP-90 mode) H.100 Bus · Data Streams 32 data streams labeled CT_D(0..31) · Clock Signals Primary bit clocks and framing signals (A clocks) Secondary bit clocks and framing signals (B clocks) Backup timing reference (CT_NETREF) Compatibility clocks (to interoperate with other telephony buses)

4.2 Single Chassis Clock Configuration

In a system, one board drives the bus clock signals. The board that drives the bus clocks is called the bus clock master. All the timing signals are passed across the bus from the clock master. All other boards reference their clocks from the bus.
In a digital system, one or more of the boards in the system are connected by digital trunks to high-quality timing references within the public telephone network. Within the digital trunk interface, an 8 KHz reference is derived from the incoming signal. The clock master is phase-locked to this 8 KHz reference so that the long-term timing of the system matches that of the public telephone network. Typically, the board that is configured as the bus clock master also interfaces to the digital trunk that is being used as the network timing reference.
In an analog system with no digital telephone network interfaces, an analog board is configured as the bus clock master using the on-board oscillator to drive the clock signals.

4.2.1 H.100 Clock Configuration

Any board that contains an interface to an external communications network can be configured as a bus clock master. A board is configured as bus clock master either at installation or under software control. Figure 58 shows the H.100 clock master driving the A clocks. Figure 58. H.100 Bus Clock Master
All other boards in an H.100 system are the bus clock slaves. Slaves reference their clocks from the bus. Figure 59. Bus Clock Slaves
An additional digital trunk can be configured as a backup network timing reference. The backup reference may be used if a failure occurs on the primary reference trunk. The backup reference is referred to as CT_NETREF on the H.100 bus. Any board that contains an interface to an external communications network can drive the backup or secondary reference. Figure 60. Backup Reference Trunk
The following table summarizes the different clock configurations for boards on the H.100 bus: H.100 Board Configuration Timing Reference Driven Clock Signal Clock Master Digital Trunk Drives A clocks. Slave(s) A clocks One slave may be configured to drive CT_NETREF, referencing a digital trunk.

4.2.2 MVIP-90 and H-MVIP Clock Configuration

On the MVIP-90 and H-MVIP busses, one board is configured as the clock master. All the timing signals are passed across the bus from the clock master. All other boards are clock slaves and reference their clocks from the bus.
All boards containing an interface to an external communications network can be configured as a bus master. Typically the clock master is configured to use the digital trunk it is connected to as the network timing reference.
An additional digital trunk can be configured as a backup network timing reference. The backup reference may be used if a failure occurs on the primary reference. The backup or secondary network reference is referred to as SEC8K.
The following table summarizes the different clock configurations for boards on the MVIP-90 bus: MVIP Board Configuration Timing Reference Driven Clock Signal Clock Master Digital Trunk Drives bus clocks. Clock Slave(s) Bus Clocks One clock slave may be configured to drive SEC8K by referencing a digital trunk.

4.3 Bus Clocking Fallback Behavior

The bus clock architecture provides system stability even during failure of external timing sources.
If the digital trunk that is serving as a source of timing reference should fail, the master clock circuit has adequate stability to maintain synchronization for many seconds per Enhanced Stratum 4 clock standards.

4.3.1 H.100 Bus Primary Reference Trunk Failure

In the event that the primary reference trunk fails, the clock master can be switched under software control to the CT_NETREF signal for its network timing reference. When the primary reference comes back, the master switches back under software control. Figure 61. Primary Reference Trunk Failure

4.3.2 MVIP-90 and H-MVIP Bus Primary Reference Trunk Failure

When a network trunk fails, the trunk will go into "red alarm" condition. Trunk monitor software should be configured to inform the application to configure an alternate timing reference to the master clock circuit.
If the backup or secondary timing reference is located on a different board than that of the master clock, then this 8 kHz reference signal is passed to the master clock circuit over the MVIP bus line SEC8K.
The clock master is then instructed by software to use the SEC8K signal. Figure 62. Clock Master Using SEC8K to Derive Clock Signals

4.4 Multi-Chassis Clock Configuration

The clocks in a multi-chassis system must all be synchronized. This means that all boards in all chassis in the system must be driven by the same clock source.
There are three independent clock signals on the MC1 bus: MC1_8K (also called 8KREF) Left clock signals Right clock signals
In the Go-MVIP: MC1 Multi-Chassis MVIP Standard, the MC1_8K clock signal is called 8KREF. The MC1_8K (8KREF) clock signal provides the source clock signal ultimately used by all the MC1 boards. Either the left or right clock signal is configured to propagate this source clock signal to the MC1 bus. This clock line (left or right) is used to control the timing in the system. The unused signal line (left or right) may be configured as a backup clock signal.
Each MC1 board in the system is configured in one of the following clock modes: Primary master The primary master synchronizes to the MC1_8K (8KREF) clock signal and generates either the left or right MC1 clocks. An MC1 system must have one and only one MC1 board configured as the primary master. This board will control the timing in the system. Secondary master The secondary master is a backup to the primary master. It drives the clock that the primary master is not driving, synchronizing to the primary master. In the event of a primary clock failure, the secondary master supplies all the necessary clocking signals. An MC1 system can have one and only one MC1 interface board selected as secondary master. The secondary master is optional. Slave All remaining MC1 boards in the system must be configured in slave mode. The slave boards monitor the designated primary master. In the event of a primary clock failure, the slave boards can be configured to automatically fall back to the secondary master for their clocking requirements.
Figure 63 shows a typical MC1 system. MC1 board 1 is configured as the primary master synchronizing to the MC1_8K (8KREF) clock and driving the left clock signals. MC1 board 2 receives the left clock signals. It is also configured as the secondary master driving the right clock signals. MC1 board 3 is configured as a slave and receives its clock signal from the left clocks driven by the primary master. Figure 63. MC1 Bus Clocking Configuration

4.4.1 MC1 Bus and MVIP Bus Clock Interaction

The clocks in a multi-chassis system must all be synchronized. As shown in Figure 64, a single digital network interface board (e.g., AG-T1) is chosen as the overall system timing reference. This network board is configured to extract the 8 KHz telephone company reference and propagate it to the MVIP bus SEC8K signal.
The MC1 board in that chassis is configured to propagate the SEC8K signal to the MC1_8K (8KREF) signal on the MC1 bus for use by the primary master. The MC1 primary master references the MC1_8K (8KREF) signal and drives the left or right clocks.
All other MC1 boards receive their clock from the left or right clock signals. Each MC1 board typically drives the MVIP bus clocks in its PC chassis. Note: While any MC1 board in the system can be configured to propagate the clock signal from the SEC8K line to the MC1_8K (8KREF) line, it is recommended that the primary master propagate the SEC8K signal. Figure 64. MC1 Clock Propagation Note: It is recommended that the SEC8K clock line for each MVIP bus be driven by a digital network board in its chassis for use as a backup timing reference.

(Page 1 of 1 in this chapter)

tech_support@nmss.com

Copyright © 1999, Natural MicroSystems, Inc. All rights reserved.