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Chapter 5

MVIP-90 and H.100 Bus Interaction

The H.100 bus is a superset of the MVIP-90 bus. The streams on the H.100 bus may be configured to be clocked at the following speeds: 2 MHz - providing 32 timeslots 4 MHz - providing 64 timeslots 8 MHz - providing 128 timeslots
H.100 streams clocked at 2 MHz are compatible with the MVIP-90 bus.
Streams can be accessed by boards on both the H.100 bus and the MVIP-90 bus using MVIP Bus Adapter.

The MVIP Bus Adapter is an adapter which connects the H.100 bus to the MVIP-90 bus in the same computer chassis (see Figure 65).
Figure 65. Connecting the H.100 Bus to MVIP-90 Bus
The MVIP Bus Adapter allows boards connected to the H.100 bus to access the MVIP-90 bus and MVIP-90 boards to access the first 16 streams of the H.100 bus.
When connecting H.100 boards to the adapter, configure the first 16 streams on the bus for MVIP-90 mode. The H.100 streams running in MVIP-90 mode are clocked at 2 MHz, each having 32 timeslots.
Figure 66. MVIP Bus Adapter Stream Mappings
In a system with both H.100 boards and MVIP-90 boards, it is recommended that one of the H.100 boards be configured as the clock master. Note: In order to use the clock fallback features in an MC1 system, the MC1 board must be configured as the MVIP bus clock master. In an MC1 system, H.100 boards are configured as clock slaves to the MVIP-90 bus. In this configuration, some H.100 bus streams are configured in MVIP-90 compatibility mode (clocked at 2 MHz) and are limited to 32 timeslots. Note: If your system contains more than 6 AG-T1 or AG-E1 boards (revision D) connected to the H.100 bus using an MVIP bus adapter, you may experience clocking errors. Using more than 8 ISA MVIP boards with an adapter, regardless of board type, may also cause clocking problems.

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