Introduction

This appendix presents the mechanical specifications for the AG-8 and AG-8/80 boards, including ISA and MVIP bus connectors, and daughterboard mechanical requirements.

The AG-8 board has:

• 128 K static RAM between host and coprocessor

• 16 MHz 80386SX coprocessor

• 512 K coprocessor DRAM

• 32 K fast static RAM between coprocessor and DSPs

• Two 28.5 MIPS TMS320C51 task processors (DSPs)

• An FMIC, which provides enhanced-compliant MVIP switching

The AG-8/80 board has:

• 128 K static RAM between host and coprocessor

• 25 MHz 80386SX coprocessor

• 512 K coprocessor DRAM

• 128 K fast static RAM between coprocessor and DSPs

• Two 40 MIPS TMS320C51 task processors (DSPs)

• An FMIC, which provides enhanced-compliant MVIP switching

The AG-8 and AG-8/80 boards are designed to meet IBM's specifications, as described in IBM's Personal Computer Hardware Reference Library publication # 6361674, Prototype Adapter. Note that these boards are 0.3" taller than the IEEE P996 ISA specification.

The MVIP bus connector is a shrouded 40-pin 3M 2540-50020B, positioned as specified in section 3 of the MVIP Reference Manual Version 1.0 (available to MVIP licensees).

Power Requirements

Environment

Regulatory Certification (USA And Canada)

MVIP Compliant Interface

The AG-8 and AG-8/80 boards provide:

• Flexible connectivity between line interfaces, DSPs, and MVIP bus.

• Switchable access to any of 512 MVIP timeslots.

• The ability to act as MVIP clock master or clock slave (software- selectable).

• Compatibility with any MVIP compliant telephony interface.

External Power Supply Requirements

For DID and E&M operation:

• Output - 48 VDC, 250 mA minimum current

• Regulation - ± 1 Volt

• Ripple - 5 mV rms. maximum

NMS recommends the TELLABS 8001 Power Supply (available from NMS) for DID and E&M applications.

The bicolor LEDs on the board face and on the end bracket provide visual feedback of proper system operation. They are shown in Figure 27:

Figure 27. LEDs on the AG-8 and AG-8/80 Boards.

D1 and D2 show the arbiter request/grant status for each DSP. D3 shows the arbiter request/grant status for the coprocessor. D3 is red when the processor has been granted access to the DSP SRAM. D3 is green when the processor is not requesting access. D4 and D5 indicate the status of the host interface; D6 indicates the state of the DSP interface.

Specific conditions for D4, D5, and D6 are:

LED	Color	Condition	Description
D4	Green	ON	SRAM is not busy.
	Green	OFF	SRAM is busy.
	Red	ON	Coprocessor is reset.
	Red	OFF	Coprocessor is unreset.
D5	Green	ON	Host owns SRAM.
	Green	OFF	Coprocessor owns SRAM.
	Red	ON	Coprocessor transmits to host.
	Red	OFF	Host transmits to coprocessor.
D6	Green	ON	Unused.
	Red	ON	The DSP section is reset.
	Red	OFF	The DSP section is unreset.

The right-most LED on the end bracket is the external power supply indicator. The other LED on the end bracket blinks during board initialization diagnostics.

DIP switch S1, shown in Figure 27, selects the AG board's base I/O address. The AG board occupies 6 contiguous I/O addresses. The base address must be unique and must not conflict with any other devices in the system.

AG boards are set to the default base address 0x02C0.