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Figure 1. Sample SS7 Test SetupNote: The SS7 link "turn up" test described in this section cannot be run by looping back two ports on a single TX board. A minimum of two TX boards, or one board and a separate piece of SS7 test equipment capable of emulating an SS7 node up through MTP layer 3, are required.
CLOCK NETA
SEC8K NONE
# T1 Framing Encoding Buildout Robbed Bit Loop Master
# -- ------- -------- -------- ---------- -----------
T1A ESF B8ZS 0 FALSE FALSE
T1B ESF B8ZS 0 FALSE FALSE
#
# Port Stream Channel Count Direction
# ----------- ----------- ------------- ----- ---------
Port1 T1A Channel0 Count1 Standard
CLOCK NETA, indicating the clock recovered from T1A should be presented onto the MVIP/H.100/H.110 bus. When two TX boards are present in a chassis, tdmcp2.txt can be used to configure board 2. Board 2 is configured with the T1s set as Loop Master. This causes board 2 to use its internal oscillator as the clock source for both T1s. This board is also configured with CLOCK BUS, indicating the TDM clock should be taken from the MVIP/H.100/H.110 bus. These configuration files will require various changes to be made when the boards are being loaded for purposes other than initial testing.
Port1 to a timeslot other than zero (timeslot zero is used solely for
framing on E1 ports and cannot be used to transport data such as SS7).
CLOCK and/or Loop Master fields should be
modified.
#Link Parameters #--------------- LINK T1 # T<n> for T1/E1/MVIP, S<n> for serial (V.35) LINK_SET 1 ADJACENT_DPC 1.1.2 # Board 2 LINK_SLC 0 MAX_CREDIT 127 MESSAGE_SIZE 272 # # Level 2 parameters # LSSU_LEN 2 END
T1 to port S1. Also you must specify one side of the link (e.g. board 1) as the DCE and the other side of the link (e.g., board 2) as the DTE. Make sure that the link configured as the DCE also has its V.35 POD port strapped for DCE operation. Likewise, the link configured as the DTE must have its V.35 POD port strapped for DTE operation. See the TX 2000/TX 3000 Installation Manual for details on configuring the V.35 POD.
[-f <filename>]
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<01/07/1998 16:17:04>
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mtp
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1
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18180
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MTP3 Link 1 Down
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Timestamp
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Task
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Board Number
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Alarm Number
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Alarm Text
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prompt> ss7load 1 CPMODEL V1.0: Copyright 1998, Natural MicroSystems Board #1 is a TX2000 Loading: E.0 TX2000 Kernel (c)1996-1997 Natural MicroSystems, Inc. 2/10/97 Loading: diag2000 Version C.1.0 12/10/97 Loading: Loading: inf Version C.4.0 12/10/97 Loading: mvip Version A.1.0 12/10/97 Loading: t1e1mgr Version A.1.0 12/10/97 Loading: mtp Version B.3.0 01/14/98 mtp2cfg: sample MTP2 configuration application version B.1.0 Jan 14 1998 mtp3cfg: sample MTP3 configuration application version B.3.0 Jan 14 1998 prompt> ss7load 2
<12/05/1997 15:51:58> mtp 1 1 Registering MTP Layer 2 <12/05/1997 15:51:58> mtp 1 1 Registering MTP Layer 3 <12/05/1997 15:51:58> mtp 1 1 Configuring MTP Layer 1 <12/05/1997 15:51:58> mtp 1 1 MTP1 Initializing. <12/05/1997 15:51:58> mtp 1 1 MTP1 General Configuration <12/05/1997 15:51:58> mtp 1 1 MTP1 Configuring link 0: TDM, External <12/05/1997 15:51:58> mtp 1 1 MTP1 Configuring link 1: TDM, External <12/05/1997 15:51:58> mtp 1 1 MTP1 Configuring link 2: TDM, External <12/05/1997 15:51:58> mtp 1 1 MTP1 Configuring link 3: TDM, External <12/05/1997 15:51:58> mtp 1 1 MTP1 Configuration Done <12/05/1997 15:51:58> mtp 1 1 Configuring MTP Layer 2 <12/05/1997 15:51:58> mtp 1 1 MTP2: General Configuration <12/05/1997 15:51:58> mtp 1 1 MTP2: Link 0 Configuration <12/05/1997 15:51:58> mtp 1 1 MTP2: Link 1 Configuration <12/05/1997 15:51:58> mtp 1 1 MTP2: Link 2 Configuration <12/05/1997 15:51:58> mtp 1 1 MTP2: Link 3 Configuration <12/05/1997 15:51:58> mtp 1 1 MTP3: Ready
<01/09/1998 09:54:21> mtp 1 1 Flushing Buffers (OPC=0) <01/09/1998 09:54:21> mtp 1 1 Starting Alignment <01/09/1998 09:54:21> mtp 1 1 IAC Rx SIO <01/09/1998 09:54:21> mtp 1 1 IAC Rx SIO <01/09/1998 09:54:21> mtp 1 1 Rx SIE (9) <01/09/1998 09:54:22> mtp 1 1 ALIGN TIMER 4 EXPIRED (Link Aligned) <01/09/1998 09:54:22> mtp 1 1 Setting link 0 ACTIVE in SigLinkAvail <01/09/1998 09:54:22> mtp 1 1 DPC 0.1.2 is now ACCESSABLE (LinkSet 1) <01/09/1998 09:54:22> mtp 1 1 Setting link 0 ACTIVE in TrafLinkAvail <01/09/1998 09:54:22> mtp 1 1 Setting link 0 ACTIVE from SLTA <01/09/1998 09:54:22> mtp 1 1 8179 MTP3 Link 0 Up <01/09/1998 09:54:21> mtp 2 1 Flushing Buffers (OPC=0) <01/09/1998 09:54:21> mtp 2 1 Starting Alignment <01/09/1998 09:54:21> mtp 2 1 IAC Rx SIO <01/09/1998 09:54:21> mtp 2 1 IAC Rx SIO <01/09/1998 09:54:21> mtp 2 1 Rx SIE (9) <01/09/1998 09:54:22> mtp 2 1 ALIGN TIMER 4 EXPIRED (Link Aligned) <01/09/1998 09:54:22> mtp 2 1 Setting link 0 ACTIVE in SigLinkAvail <01/09/1998 09:54:22> mtp 2 1 DPC 0.1.2 is now ACCESSABLE (LinkSet 1) <01/09/1998 09:54:22> mtp 2 1 Setting link 0 ACTIVE in TrafLinkAvail <01/09/1998 09:54:22> mtp 2 1 Setting link 0 ACTIVE from SLTA <01/09/1998 09:54:22> mtp 2 1 8179 MTP3 Link 0 Up
Align Timer 2 Expired and Alignment not possible as shown in the following example:
<01/09/1998 09:49:58> mtp 2 1 Starting Alignment <01/09/1998 09:49:58> mtp 2 1 Layer1: AERM Threshold Reached <01/09/1998 09:49:58> mtp 2 1 Alignment Aborting <01/09/1998 09:50:10> mtp 2 1 ALIGN TIMER 2 EXPIRED, QLen=0 iacSt=8 <01/09/1998 09:50:10> mtp 2 1 LinkFailure : Alignment Not Possible <01/09/1998 09:50:10> mtp 2 1 Flushing Buffers (OPC=0) <01/09/1998 09:50:11> mtp 2 1 8180 MTP3 Link 0 Down
Align Timer 4 Expired (Link Aligned) followed by an MTP alarm indicating that the link is down, as shown in the following example:
<01/09/1998 09:54:21> mtp 1 1 Starting Alignment <01/09/1998 09:54:21> mtp 1 1 IAC Rx SIO <01/09/1998 09:54:21> mtp 1 1 IAC Rx SIO <01/09/1998 09:54:21> mtp 1 1 Rx SIE (9) <01/09/1998 09:54:22> mtp 1 1 ALIGN TIMER 4 EXPIRED (Link Aligned) <01/09/1998 09:54:22> mtp 1 1 8180 MTP3 Link 0 Down
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