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Appendix B

TDM Configuration Utility

Introduction

Text Configuration File Creation

: Bus Timing
: T1/E1 Configuration Options
: Channel Definition Entry
: Configuration Binary File Generation
: Configuration Download

Introduction

The TDM configuration utility is used to set the default MVIP and T1/E1 configuration of a TX board with MVIP and/or T1/E1 adapters. This utility is also used to define dedicated data channels from the MVIP or T1/E1 interfaces.
Dedicated data channels are pre-configured by creating an offline database and downloading it to the CPK kernel when the TX board is loaded. Offline database creation consists of creating the configuration text file, compiling the text file to create the configuration binary image, and downloading the binary image to the TX kernel. These steps are detailed in the following subsections. Note: Each TX board must have its own separate TDM configuration database.
Once TDM data channels are defined in the configuration database, other NMS communication software products, such as the SS7 Protocol Stack, may be configured to utilize these channels as communication ports. This is done by selecting the TDM port type in the appropriate software product's configuration utility.

Text Configuration File Creation

A text file (hereafter referred to as the tdmcfg.txt file) is prepared containing a description of each dedicated data channel: the TX port that it is assigned to, the TDM stream that it occupies, the first timeslot on that TDM stream that it occupies, the number of timeslots used, and the direction (described below). The tdmcfg.txt file also configures the clocking associated with the MVIP bus adapter interface as well as the configuration of the T1/E1 interfaces. The following examples show sample tdmcfg.txt configurations, depending on the TX board used: ########################################################################### # EXAMPLE T1 interface: ########################################################################### # CLOCK NETA # SEC8K NONE #-------------------------------------------------------------------------- # T1 Framing Encoding Buildout Robbed Bit Loop Master # --- ------- -------- -------- ---------- ----------- # T1A ESF B8ZS 0 FALSE FALSE # T1B ESF B8ZS 0 FALSE FALSE #-------------------------------------------------------------------------- # TX Port Stream Channel Count Direction # ------ -------- --------- ------- ----------- # Port1 T1A Channel0 Count1 Standard ########################################################################### # EXAMPLE E1 interface: 16 port configuration ########################################################################### # CLOCK NETA # SEC8K NONE #-------------------------------------------------------------------------- # E1 Framing Encoding Buildout Robbed Bit Loop Master # --- ------- -------- -------- ---------- ----------- # E1A CCS HDB3 4 FALSE FALSE # E1B CCS HDB3 4 FALSE FALSE #-------------------------------------------------------------------------- # TX Port Stream Channel Count Direction # ------ -------- ----------- ------- ----------- # Port1 E1A Channel1 Count1 Standard # Port2 E1A Channel2 Count1 Standard # Port3 E1A Channel3 Count1 Standard # Port4 E1A Channel4 Count1 Standard # Port5 E1A Channel5 Count1 Standard # Port6 E1A Channel6 Count1 Standard # Port7 E1A Channel7 Count1 Standard # Port8 E1A Channel8 Count1 Standard # Port9 E1B Channel1 Count1 Standard # Port10 E1B Channel2 Count1 Standard # Port11 E1B Channel3 Count1 Standard # Port12 E1B Channel4 Count1 Standard # Port13 E1B Channel5 Count1 Standard # Port14 E1B Channel6 Count1 Standard # Port15 E1B Channel7 Count1 Standard # Port16 E1B Channel8 Count1 Standard ########################################################################### # EXAMPLE MVIP interface: ########################################################################### # CLOCK BUS # SEC8K NONE # BUS MVIP #-------------------------------------------------------------------------- # TX Port Stream Channel Count Direction # ------- --------- ---------- ------- ----------- # Port1 Stream0 Channel0 Count32 Standard # Port2 Stream1 Channel2 Count1 Reverse # Port3 Stream2 Channel0 Count32 Standard # Port4 Stream3 Channel31 Count1 Reverse ########################################################################### # EXAMPLE H.100/H.110 interface: ########################################################################### # CLOCK BUS # SEC8K NONE # BUS H100 #-------------------------------------------------------------------------- # TX Port Stream Channel Count Direction # ------- --------- ---------- ------- ----------- # Port1 Stream0 Channel0 Count32 Standard # Port2 Stream2 Channel2 Count1 Reverse # Port3 Stream4 Channel0 Count32 Standard # Port4 Stream16 Channel127 Count1 Reverse Note: These options may be overridden at run time by application requests, typically when a circuit-switching application is combined with dedicated data channels in the same system. These entries are primarily intended to allow the data channels to operate with no application intervention (for example, with NMS Gateway products) when no circuit-switching application is present.
Individual configuration fields are described in more detail in the following sections.

Bus Timing

The bus timing entry describes the clocking configuration for the MVIP bus adapter interface. Three timing entries can be specified.
The TIMING field specifies the mode for the main MVIP bus clock signals (/C4, /F0, C2). The following table lists acceptable values and provides a description for each: Value Description BUS Adapter gets timing signals from the MVIP/H.100 bus (default). MASTER Adapter drives the MVIP/H.100 bus clock signals from its internal clock. SEC8K Adapter gets timing signals from the MVIP/H.100 bus SEC8K signal as the clock reference input. NETA Adapter drives the MVIP/H.100 bus clock signals using T1/E1 adapter interface A's 8KHz clock signal as the clock reference input. NETB Adapter drives the MVIP/H.100 bus clock signals using T1/E1 adapter interface B's 8KHz clock signal as the clock reference input.
The SEC8K field specifies the mode for the MVIP bus secondary 8KHz reference signal. Possible values are: Value Description NONE SEC8K not driven. MASTER Adapter drives the SEC8K signal from its internal clock. NETA Adapter drives the SEC8K signal from T1/E1 adapter interface A's 8KHz clock signal. NETB Adapter drives the SEC8K signal from T1/E1 adapter interface B's 8KHz clock signal.
The BUS field specifies which type of stream numbering is to be used. Possible values are: Value Description MVIP MVIP bus stream numbering. Full-duplex connections: stream (0..7) paired with (8..15) H100 H.100/H.110 bus stream numbering. Full-duplex connections: stream (0..30) paired with (1..31)

Value	Description
`BUS`	Adapter gets timing signals from the MVIP/H.100 bus (default).
`MASTER`	Adapter drives the MVIP/H.100 bus clock signals from its internal clock.
`SEC8K`	Adapter gets timing signals from the MVIP/H.100 bus SEC8K signal as the clock reference input.
`NETA`	Adapter drives the MVIP/H.100 bus clock signals using T1/E1 adapter interface A's 8KHz clock signal as the clock reference input.
`NETB`	Adapter drives the MVIP/H.100 bus clock signals using T1/E1 adapter interface B's 8KHz clock signal as the clock reference input.

Value	Description
`NONE`	SEC8K not driven.
`MASTER`	Adapter drives the SEC8K signal from its internal clock.
`NETA`	Adapter drives the SEC8K signal from T1/E1 adapter interface A's 8KHz clock signal.
`NETB`	Adapter drives the SEC8K signal from T1/E1 adapter interface B's 8KHz clock signal.

Value	Description
`MVIP`	MVIP bus stream numbering. Full-duplex connections: stream (0..7) paired with (8..15)
`H100`	H.100/H.110 bus stream numbering. Full-duplex connections: stream (0..30) paired with (1..31)

T1/E1 Configuration Options

The T1/E1 configuration line consists of an identifier indicating which T1/E1 circuit (A or B) is being configured followed by parameters specifying the Framing, Line Encoding, Line Buildout (T1 only), Robbed Bit signaling, and Loop Master (timing source) configuration for this circuit.
Framing Options determine the framing formats to be used for this circuit. Valid entries include: Value Description None Do not configure this T1/E1 circuit. D4 [T1] D4 (193S) Framing. ESF [T1] Extended Superframe Format. CCS [E1] Frame alignment only (no multiframe alignment) CAS [E1] Standard frame alignment with Channel Associated Signaling (timeslot 16) multiframe alignment (but no CRC4). CCSCRC4 [E1] Standard frame alignment with CRC4 multiframe alignment (but no CAS). CASCRC4 [E1] Standard frame alignment with both Channel Associated Signaling (timeslot 16) and CRC4 multiframe alignment.
Encoding Options determine line encoding and zero suppression mechanisms to be used for this circuit. Valid entries include: Value Description NONE No encoding. NOZCS [T1 or E1] AMI encoding with no zero code suppression. B7ZS [T1] Bit Seven Zero Stuffing. B8ZS [T1] Bipolar Eight Zero Substitution. HDB3 [E1] High Density Bipolar Order 3.
Buildout Options determine line buildouts to be used for this circuit. Acceptable values include: 0-4 T1 0 0 to 133 feet 1 133 to 266 feet 2 266 to 399 feet 3 399 to 533 feet 4 533 to 655 feet 1,4,5,7 E1 1 120 Ohm normal 4 120 Ohm with protection resistors (default) 5 120 Ohm with 14dB return loss 7 120 Ohm with 27dB return loss
Robbed Bit Flag indicates whether Robbed Bit Signaling is used by the TX board on this circuit (T1 only - ignored for E1 circuits). Must be either TRUE or FALSE (default).
Loop Master Flag indicates whether this interface is the master of loop timing for this circuit. Must be either TRUE or FALSE.

Value	Description
`None`	Do not configure this T1/E1 circuit.
`D4`	[T1] D4 (193S) Framing.
`ESF`	[T1] Extended Superframe Format.
`CCS`	[E1] Frame alignment only (no multiframe alignment)
`CAS`	[E1] Standard frame alignment with Channel Associated Signaling (timeslot 16) multiframe alignment (but no CRC4).
`CCSCRC4`	[E1] Standard frame alignment with CRC4 multiframe alignment (but no CAS).
`CASCRC4`	[E1] Standard frame alignment with both Channel Associated Signaling (timeslot 16) and CRC4 multiframe alignment.

Value	Description
`NONE`	No encoding.
`NOZCS`	[T1 or E1] AMI encoding with no zero code suppression.
`B7ZS`	[T1] Bit Seven Zero Stuffing.
`B8ZS`	[T1] Bipolar Eight Zero Substitution.
`HDB3`	[E1] High Density Bipolar Order 3.

0-4	T1
0	0 to 133 feet
1	133 to 266 feet
2	266 to 399 feet
3	399 to 533 feet
4	533 to 655 feet

1,4,5,7	E1
1	120 Ohm normal
4	120 Ohm with protection resistors (default)
5	120 Ohm with 14dB return loss
7	120 Ohm with 27dB return loss

Channel Definition Entry

The channel definition entry describes the characteristics of each dedicated data channel. The following table provides a list of valid field entries: Value Description Portn Identifies the TX port assigned to this data channel, where n is an integer between 1 and 16. Streamn Identifies the MVIP or T1/E1 stream that this channel occupies, where n is one of the following: · 0 - 7 for MVIP streams · 0 - 30 (even numbers only) for H100 T1/E1 streams are identified using the T1A/E1A/T1B/E1B fields. Channeln Refers to the starting channel number, where n is one of the following: · 0 - 7 for MVIP · 0 - 127 for H100 · 0 -23 for T1 · 1 - 31 (0 is used for framing) for E1 Countn Number of timeslots allocated to the channel, where n is an integer between 1 and 32 (MVIP or H100). For subrates (56Kb or 48Kb) on a single DS0: · If count is 56, a single channel with a 56Kb subrate is allocated. · If count is 48, a single channel with a 48Kb subrate is allocated. Direction T1/E1 channels are always STANDARD. · Standard: DSon is the input stream, and DSin is the output stream. · Reverse: DSin is the input stream, and DSon is the output stream.

Value	Description
`Port`n	Identifies the TX port assigned to this data channel, where n is an integer between 1 and 16.
`Stream`n	Identifies the MVIP or T1/E1 stream that this channel occupies, where n is one of the following: · 0 - 7 for MVIP streams · 0 - 30 (even numbers only) for H100 T1/E1 streams are identified using the T1A/E1A/T1B/E1B fields.
`Channel`n	Refers to the starting channel number, where n is one of the following: · 0 - 7 for MVIP · 0 - 127 for H100 · 0 -23 for T1 · 1 - 31 (0 is used for framing) for E1
`Count`n	Number of timeslots allocated to the channel, where n is an integer between 1 and 32 (MVIP or H100). For subrates (56Kb or 48Kb) on a single DS0: · If count is 56, a single channel with a 56Kb subrate is allocated. · If count is 48, a single channel with a 48Kb subrate is allocated.
`Direction`	T1/E1 channels are always `STANDARD`. · `Standard`: DSon is the input stream, and DSin is the output stream. · `Reverse`: DSin is the input stream, and DSon is the output stream.

Configuration Binary File Generation

The configuration binary file is generated by running the configuration utility on this file. The is done with the command tdmcfg -i filename
where filename is the name of the text file from which the binary file is created.
The TDM Configuration utility will generate 2 files: File name Description filename.bin Binary configuration file. filename.dbg Text representation of the binary file.

File name	Description
`filename.bin`	Binary configuration file.
`filename.dbg`	Text representation of the binary file.

Configuration Download

The configuration is downloaded using the standard cplot utility with the -g option as shown: cplot -g TDM -f filename -c board
where filename is the binary file that was created in the previous section and board is the TX board number to which the configuration is downloaded. Note: This must be downloaded before any tasks which might attempt to use the specified data channels.

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