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Chapter 1

Introduction

1.1 Introduction

1.2 Overview

: 1.2.1 Terminology

1.3 Software Architecture

1.4 T1/E1 and MVIP Libraries

: 1.4.1 T1/E1 Manager Task
: 1.4.2 MVIP/H.100/H.110 Manager Task

1.5 PSTN Interface Adapters

1.6 T1/E1 and MVIP API Services

: 1.6.1 Circuit Switching
: 1.6.2 Dedicated Data Channels

1.1 Introduction

The T1/E1/MVIP Interface Adapters Developer's Reference Manual describes the functions of the Dual T1/Dual E1 and MVIP/H.100/H.110 interface adapters and the software development tools available for building applications and systems based on the TDM processing facilities. Note: The term "MVIP" is used throughout this document to refer to the MVIP-90 TDM interface, as well as the H.100/H.110 interface.

1.2 Overview

The TX series of communication processors support a set of optional hardware and software modules for processing of time division multiplexed (TDM) digital data, audio, and/or video streams:
This manual describes the functions of these modules and the software development tools available for building applications and systems based on the TDM processing facilities.

1.2.1 Terminology

The following terminology is used to describe the functionality and operating modes of the T1/E1 and MVIP/H.100/H.110 interface software: This term... Refers to the following... Channel Channels are the individual physical communication paths from the TX board to other endpoints. Some physical interfaces, such as the MVIP and T1/E1 interfaces, support multiple channels. Others, such as the serial and Ethernet interfaces, support a single channel. Streams Streams are groups of channels combined on a single set of signals through time division multiplexing (TDM). Each T1 or E1 line is a TDM stream. The MVIP bus is actually 8 TDM streams of 32 channels each and the H.100/H.110 bus is actually 32 streams of 128 channels. Timeslot Each channel on a TDM stream is also called a timeslot. On TX boards, each time-slot on a TDM stream forms a 64 Kbps DS0 channel. Thus, a pair of timeslots, one in each direction, forms a full-duplex 64 Kbps DS0 channel. Hyperchannel TDM timeslots may be grouped together to form higher rate channels called hyperchannels. For example, 6 full-duplex 64 Kbps timeslots might be grouped together to form a single 384 Kbps full-duplex channel. On a TX board, a hyperchannel is configured by specifying a range of timeslots (i.e., they must be contiguous). Since a hyperchannel corresponds to a single communication path and a single protocol instance (at the link layer), it is really just a channel; so, for the rest of this document, channels and hyperchannels will not be differentiated. Ports Logical entities which define paths, or protocol instances, between TX software entities and peers at other endpoints. Ports are mapped onto physical channels by a combination of system rules and system configuration. There are several different types of ports, generally corresponding to the different physical interface types. In addition, certain link-level protocols may provide additional multiplexing capability such that a single physical channel may be used to provide many logical ports.

This term...	Refers to the following...
Channel	Channels are the individual physical communication paths from the TX board to other endpoints. Some physical interfaces, such as the MVIP and T1/E1 interfaces, support multiple channels. Others, such as the serial and Ethernet interfaces, support a single channel.
Streams	Streams are groups of channels combined on a single set of signals through time division multiplexing (TDM). Each T1 or E1 line is a TDM stream. The MVIP bus is actually 8 TDM streams of 32 channels each and the H.100/H.110 bus is actually 32 streams of 128 channels.
Timeslot	Each channel on a TDM stream is also called a timeslot. On TX boards, each time-slot on a TDM stream forms a 64 Kbps DS0 channel. Thus, a pair of timeslots, one in each direction, forms a full-duplex 64 Kbps DS0 channel.
Hyperchannel	TDM timeslots may be grouped together to form higher rate channels called hyperchannels. For example, 6 full-duplex 64 Kbps timeslots might be grouped together to form a single 384 Kbps full-duplex channel. On a TX board, a hyperchannel is configured by specifying a range of timeslots (i.e., they must be contiguous). Since a hyperchannel corresponds to a single communication path and a single protocol instance (at the link layer), it is really just a channel; so, for the rest of this document, channels and hyperchannels will not be differentiated.
Ports	Logical entities which define paths, or protocol instances, between TX software entities and peers at other endpoints. Ports are mapped onto physical channels by a combination of system rules and system configuration. There are several different types of ports, generally corresponding to the different physical interface types. In addition, certain link-level protocols may provide additional multiplexing capability such that a single physical channel may be used to provide many logical ports.

1.3 Software Architecture

The TX host application development environment consists of a series of API libraries that enable the application programmer to configure and control the various protocol engines loaded on the TX boards. This manual describes the T1/E1/MVIP API. Figure 1. TX Software Architecture Note: Always use the structure packing compile option when compiling source code using these libraries and APIs.

1.4 T1/E1 and MVIP Libraries

The T1/E1 and MVIP APIs provide high-level interfaces for host applications to control the MVIP/H.100/H.110 switch fabric and T1/E1 interfaces. The MVIP API is compatible with the MVIP-90/MVIP-95 software standards with some extensions. The T1/E1 API allows the host application to configure, monitor the status of, and collect performance statistics for the T1/E1 interfaces. The API routines utilize the services of the MVIP/H.100/H.110 and T1/E1 manager tasks on the TX board through the standard CPI driver and the DPR channels dedicated for MVIP/H.100/H.110 and T1/E1 control messages.
These APIs provide simple synchronous interfaces to the MVIP/H.100/H.110 and T1/E1 manager tasks. They issue requests and wait for responses from the TX board, blocking the calling application before returning control to the application.

1.4.1 T1/E1 Manager Task

The T1/E1 manager is a standard CPK/OS task that provides the interface from the host PC (and, optionally, other tasks) to the T1/E1 device drivers. The T1/E1 device driver provides the interface for configuring, conditioning, monitoring, and sending/receiving signaling information (channel associated signaling) on the T1/E1 channels. The T1/E1 manager translates requests from the host application through the DPR T1/E1 control channel into low-level driver requests. The T1/E1 manager also monitors each line for alarm and out-of-service states (and, when robbed-bit signaling is employed, signaling state of each T1/E1 channel) and reports changes to the host application through unsolicited messages on the T1/E1 status channel.

1.4.2 MVIP/H.100/H.110 Manager Task

The MVIP/H.100/H.110 manager is a standard CPK/OS task that provides the interface from the host PC (and, optionally, other tasks) to the MVIP/H.100/H.110 device driver. The MVIP/H.100/H.110 device driver accepts commands from a task (such as the TDM manager) or other kernel modules for managing connections through the switch fabric. The MVIP/H.100/H.110 manager translates requests from the host PC through the DPR MVIP/H.100/H.110 control channel into low-level driver requests. A response is returned over the same DPR channel for each request received.

1.5 PSTN Interface Adapters

The TX board communication processors support the following (optional) interfaces for transmitting and receiving digital data, audio, and video signals to and from public switched telephone networks: Adapter Function MVIP/H.100/H.110 Bus Interface Gives the TX board access to the MVIP/H.100/H.110 bus through a non-blocking digital timeslot switch. The MVIP/H.100/H.110 bus adapter is an enhanced switching-compliant device that can be used to make connections between the MVIP/H.100/H.110 bus, optional T1/E1 interfaces, and on-board serial communication controllers. The MVIP/H.100/H.110 bus adapter can be used by itself to allow the TX board to perform protocol processing on streams routed from other network interface boards through the MVIP/H.100/H.110 bus or in conjunction with the dual T1/E1 adapters described below (use of the dual T1/E1 adapters requires use of the MVIP/H.100/H.110 bus adapter). Dual T1 Interface Provides a flexible interface for terminating T1 circuits for protocol processing by the TX board serial communication controllers or for switching to/from other boards through the MVIP/H.100/H.110 bus adapter. It is ideally suited for data and common channel signaling (SS7) applications. The dual T1 adapter provides a DSX-1 type interface. It may be connected to the public switched telephone network through an external channel service unit (CSU) or may be directly connected to other local equipment providing a compatible interface. In the case of a direct local connection, the TX board T1 lines can be independently configured as either the loop master (timing source of the circuit) or as the loop slave (deriving clocking from the circuit). The T1 lines can also be configured with different framing and/or line coding options if desired. Dual E1 Interface Provides two E1 (CEPT) compliant line interfaces. Like the T1 adapter, it can be used in conjunction with the TX board's protocol processing capabilities and Natural MicroSystems' protocol processing software (such as the SS7 stack) to create powerful data and/or common channel signaling applications. The E1 lines can be independently configured for standard FAS, CRC4, and/or CAS (channel associated signaling) framing formats and AMI or HDB3 line coding formats. Each line can be optionally configured as the timing source (loop master) of the circuit or as the loop slave, deriving clocking from the circuit.

Adapter	Function
MVIP/H.100/H.110 Bus Interface	Gives the TX board access to the MVIP/H.100/H.110 bus through a non-blocking digital timeslot switch. The MVIP/H.100/H.110 bus adapter is an enhanced switching-compliant device that can be used to make connections between the MVIP/H.100/H.110 bus, optional T1/E1 interfaces, and on-board serial communication controllers. The MVIP/H.100/H.110 bus adapter can be used by itself to allow the TX board to perform protocol processing on streams routed from other network interface boards through the MVIP/H.100/H.110 bus or in conjunction with the dual T1/E1 adapters described below (use of the dual T1/E1 adapters requires use of the MVIP/H.100/H.110 bus adapter).
Dual T1 Interface	Provides a flexible interface for terminating T1 circuits for protocol processing by the TX board serial communication controllers or for switching to/from other boards through the MVIP/H.100/H.110 bus adapter. It is ideally suited for data and common channel signaling (SS7) applications. The dual T1 adapter provides a DSX-1 type interface. It may be connected to the public switched telephone network through an external channel service unit (CSU) or may be directly connected to other local equipment providing a compatible interface. In the case of a direct local connection, the TX board T1 lines can be independently configured as either the loop master (timing source of the circuit) or as the loop slave (deriving clocking from the circuit). The T1 lines can also be configured with different framing and/or line coding options if desired.
Dual E1 Interface	Provides two E1 (CEPT) compliant line interfaces. Like the T1 adapter, it can be used in conjunction with the TX board's protocol processing capabilities and Natural MicroSystems' protocol processing software (such as the SS7 stack) to create powerful data and/or common channel signaling applications. The E1 lines can be independently configured for standard FAS, CRC4, and/or CAS (channel associated signaling) framing formats and AMI or HDB3 line coding formats. Each line can be optionally configured as the timing source (loop master) of the circuit or as the loop slave, deriving clocking from the circuit.

1.6 T1/E1 and MVIP API Services

The following sections describe services provided by the T1/E1 and MVIP APIs.

1.6.1 Circuit Switching

The circuit switching service provides MVIP/H.100/H.110-enhanced switching between any pair of timeslots on the T1/E1 and/or MVIP interfaces. This includes connections between any MVIP/H.100/H.110 bus timeslot and any T1/E1 timeslot, between any two MVIP/H.100/H.110 timeslots, and between any two T1/E1 timeslots on the same or different T1 interfaces (without using any MVIP/H.100/H.110 bus timeslots).

1.6.2 Dedicated Data Channels

The circuit switching service allows timeslots from either T1/E1 interfaces or the MVIP/H.100/H.110 bus to be nailed-up to serial communication controllers on the TX board main or slave 68360 processors to form dedicated data channels. These may be individual 56 or 64 Kbps Ds0 channels or ranges of timeslots may be grouped together to form higher bandwidth hyperchannels. Other NMS communication software products may then be configured to operate on these channels.
Circuit switched and nailed-up timeslots may be mixed on the same T1/E1 interface and on the MVIP/H.100/H.110 bus. For example, a single T1 interface may consist of a single timeslot nailed up to a 68360 serial communication controller carrying SS7 (out of band) signaling data (processed by the NMS SS7 software product) and 23 circuit switched voice/data channels under control of an application on the host PC. The host application instructs the TX board to make connections between the T1/E1 timeslots and the MVIP/H.100/H.110 bus (or other T1/E1 timeslots) based on signaling messages received on the SS7 data channel. Note: When a configuration consists of both circuit switched and nailed-up timeslots, certain application operations, such as resetting the entire switch block, have a slightly different meaning. For the TX 2000 and TX 3000 boards, these operations are performed only on the circuit-switched timeslots (where applicable). The nailed-up timeslots remain intact. For the TX 3220 and TX 3220C boards, all circuit-switched and nailed-up timeslots are reset.

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