Introduction

CT Bus Clocking Overview

Clock Masters and Clock Slaves

Timing References

NETREF

Fallback Timing References

Secondary Clock Masters

Clock Fallback Procedure

Clock Signal Summary

Configuring Clocking in your System

Configuring the Primary Clock Master

Configuring the Secondary Clock Master

Configuring Clock Slaves

Configuring Standalone Boards

Configuring NETREF (NETREF1) and NETREF2

Example: Multi-Board System

Introduction

If your boards are connected to each other on the CT bus, you will need to set up a bus clock to synchronize communications between the boards connected to the bus. In addition, to provide redundant and fault-tolerant clocking on the bus, you can configure alternative (fallback) clock sources to provide the clock signal if the primary source fails.

CT bus clocking is configured for each board, using keywords.

This appendix:

• Describes how H.100/H.110 clocking operates

• Describes auto-fallback behavior

• Explains how to configure clocking for the boards in your system using OAM keywords

For additional information on clock configuration, refer to the Getting Started with MVIP Switching manual and the ECTF H.110 Hardware Compatibility Specification: CT Bus R1.0. For more information on retrieving and setting OAM keyword values, refer to the OAM Service Developer's Reference Manual.

CT Bus Clocking Overview

The following section provides a comprehensive overview of CT bus clocking and auto-fallback.

This section covers H.100/H.110 clocking as described in the ECTF H.110 Hardware Compatibility Specification: CT Bus R1.0. Not all boards support this specification completely. For information on setting up clocking with a particular board type, refer to the board documentation.

Note: Hardware clocking procedures are not transparent to the application. In addition to configuring clocking, the application must monitor for various clocking situations (discussed in this appendix) and take appropriate action when required.

Clock Masters and Clock Slaves

In order to synchronize data transfer from device to device across the H.100 bus or H.110 bus, devices on the bus must be phase-locked to a high-quality 8 MHz clock and 8 kHz frame pulse. These signals together are referred to as a CT bus clock.

One board on the bus generates (drives) the clock. This board is called the clock master. All other boards use this clock as a timing reference by which they synchronize their own internal clocks. These boards are called clock slaves. (See Figure 15.)

Note: Not all boards can serve as clock masters. For specifics, refer to your board documentation.

Figure 15. Clock Master and Clock Slaves

Two CT bus clocks can run simultaneously on the bus. They are called A_CLOCK and B_CLOCK. The clock master can drive either one. When you set up CT bus clocking, choose one of these clocks for your master and slaves. The other one is a redundant signal, that can be used by a secondary clock master (see below).

In Figure 16, the system is set up to use A_CLOCK:

Figure 16. System Using A_CLOCK

Timing References

To drive its CT bus clock, a clock master takes a reference signal, extracts the frequency information, defines a phase reference at the extracted frequency, and "broadcasts" this information as A_CLOCK or B_CLOCK. This reference signal is called a timing reference. When you set up a clock master, you specify what source the board will use as its timing reference.

Note: Not all timing references are supported by all boards. For details on your board models, refer to your board-specific documentation.

The timing reference signal may originate in either of two places:

• It may originate within the public network, and enter the system through a digital trunk. This is called a NETWORK timing reference (See Figure 17.)
  
  Figure 17. Timing Reference from NETWORK

• In a system with no digital telephone network interfaces, an on-board oscillator can be used as the timing reference to drive the clock signals. (See Figure 18.) This is called an OSC timing reference. OSC should be used only if there is no external clock source available.
  
  Figure 18. Timing Reference from OSC

NETREF

The timing reference used by a clock master to drive the CT bus clock may originate from an oscillator or trunk connected to another device in the system. In this case, the timing reference signal is carried over the CT bus to the clock master, which derives the clock signal and drives the clock for the slaves. (See Figure 19.)

Figure 19. Timing Reference from Other Device

The channel over which the timing reference signal is carried to the clock master is called NETREF. (See Figure 20.)

Figure 20. NETREF

On the H.110 bus, a second timing reference signal can be carried on a fourth channel, called NETREF2. NETREF is referred to as NETREF1 in this case. (See Figure 21.)

Figure 21. NETREF2

Note: Not all board models support NETREF or NETREF2. For details on your board models, refer to your board-specific documentation.

Fallback Timing References

Boards can optionally be assigned a backup (fallback) timing reference, which it can use if its primary timing reference fails. For a clock master, the source for the fallback timing reference should NOT be the source currently used by the clock master for its primary timing reference. Fallback timing references are assigned at startup using keywords, or later using switching commands.

For example, if a clock master's primary timing reference source is a NETWORK signal from one of its trunks, the fallback timing reference source can be a NETWORK signal from another one of its trunks, or a signal from NETREF1, NETREF2 (if H.110), or OSC. In Figure 22, the fallback timing reference source is NETREF1.

Figure 22. Fallback Timing Reference

The ability of a board to automatically switch to its fallback timing reference if its primary timing reference fails is called auto-fallback. This feature can be enabled or disabled.

Note: Not all boards support auto-fallback. For details on your board models, refer to your board-specific documentation.

Secondary Clock Masters

You can set up a second device to be used as a backup, or secondary clock master, if the primary clock master stops driving its CT bus clock (because both of its timing references failed, or it was hot-swapped out, or for some other reason). For the secondary clock master to work:

1. It must receive its primary timing reference from the CT bus clock driven by the primary clock master (either A_CLOCK or B_CLOCK).

2. It must drive the CT bus clock not driven by the primary master. For example, if the primary clock master is driving A_CLOCK, the secondary clock master must drive B_CLOCK.

3. It must have a fallback timing reference. This timing reference must be different than the primary clock master's primary and fallback timing references.

4. All other slave boards must be set up so their fallback timing references are the CT bus clock driven by the secondary clock master.

A sample secondary clock master configuration is shown in Figure 23:

Figure 23. Fallback Timing Reference for Secondary Clock Master

Note: Not all boards can act as secondary master. For details on your board models, refer to your board-specific documentation.

With a secondary clock master, auto-fallback works as follows:

1. As long as the primary clock master is driving its CT bus clock, the secondary clock master acts as a slave to the primary clock master. However, the secondary master also drives the CT bus clock not driven by the primary master (for example, B_CLOCK if the primary master is driving A_CLOCK).

2. If the primary clock master stops driving its CT bus clock, all slaves (including the secondary clock master) lose their primary timing reference.

3. This triggers the secondary master to auto-fallback to its fallback timing reference.

4. This also triggers other slaves to auto-fallback to the CT bus clock driven by the secondary clock master.

5. The secondary master and slaves will not switch back to the primary timing reference without software intervention.

6. The primary master becomes a slave to the clock driven by the secondary master.

The secondary clock master is now clock master for the whole system. (See Figure 24.)

Figure 24. Secondary Clock Master Driving System

Clock Fallback Procedure

The diagrams on the following pages illustrate the clock fallback procedures for the primary clock master, secondary clock master, and slave.

The shaded areas in the diagrams below indicate conditions and behaviors which are not strictly defined or described in the ECTF H.110 Hardware Compatibility Specification: CT Bus R1.0 specification.

Note: The diagrams describe the actions taken by most NMS board models in these situations. For specifics on a particular board, refer to the board manual.

Figure 25 illustrates the role of the primary clock master in clock fallback. Note that if the primary master loses its primary timing reference and switches to its secondary reference, and then the primary reference is established again, the master switches back to the primary timing reference.

Figure 25. Clock Fallback Behavior (Primary Clock Master)

Figure 26 illustrates the role of the secondary clock master in clock fallback. The secondary master takes over only if the primary master loses both of its timing references. The secondary master continues to drive the clock for the whole system until software intervention by an application.

Figure 26. Clock Fallback Procedure (Secondary Clock Master)

Figure 27 illustrates the behavior of the slaves in clock fallback. If the primary master loses both of its timing references and is no longer driving the clock, all slaves attempt to switch over to the other CT bus clock, driven by the secondary master. They will continue to use this clock until reset by an application.

Figure 27. Clock Fallback Procedure (Slaves)

Clock Signal Summary

The following table summarizes the reference clocks that a clock master can drive:

Clock	Details
A_CLOCK	The set of primary bit clocks (CT8A) and framing signals(CTFrameA). The CT8A signal is a 8 MHz clocking reference for transferring data over the CT bus. The CTFrameA provides a low going pulse signal every 1024 (8 MHz) clock cycles.
B_CLOCK	The set of secondary bit clocks (CT8B) and framing signals(CTFrameB). The CT8B signal is a 8 MHz clocking reference for transferring data over the CT bus. The CTFrameB provides a low going pulse signal every 1024 (8 MHz) clock cycles.

The following table summarizes the timing references that a clock master can use:

Timing Reference	Details
NETWORK	The timing signal from a digital trunk attached to the clock master board. Within the digital trunk interface, an 8 kHz reference is derived from the frequency of the incoming signal. The clock master is frequency-locked to this 8 kHz reference so that the long-term timing of the system matches that of the public telephone network. Note: No timing signal is available from an analog trunk.
NETREF / NETREF1	The CTNETREF_1 signal. Can be 8 kHz, 1.544 MHz, or 8 MHz, but NMS recommends using only 8 kHz signals for most boards.
NETREF2	(H.110 only) The CTNETREF_2 signal. Can be 8 kHz, 1.544 MHz, or 8 MHz, but NMS recommends using only 8 kHz signals for most boards.
OSC	Clock signal derived from an oscillator on the clock master board. Note: Use this timing reference source only if no network timing references are available.

Note: Not all signals are supported by all boards. For details on your board models, refer to your board-specific documentation.

Configuring Clocking in your System

To configure clocking in your system, specify each board's role in the board's managed object, using keywords. The following sections describe how to use board configuration keywords to specify clocking configurations on multiple-board systems.

Note: Not all boards can act as primary or secondary master. For details on your board models, refer to your board-specific documentation.

Configuring the Primary Clock Master

The primary clock master drives a CT bus clock used as the primary timing reference by all other boards connected to the CT bus. Use the following keywords to configure the primary clock master:

Keyword	Description
Clocking.HBus.ClockMode	Specifies the CT bus clock that the board drives. For the primary clock master, specify: · MASTER_A for A_CLOCK · MASTER_B for B_CLOCK
Clocking.HBus.ClockSource	Specifies the primary timing reference for the board. For the primary clock master, set to any of the following: · NETREF to use NETREF (also known as NETREF1 in H.110 parlance) · NETREF2 to use NETREF2 (H.110 only) · NETWORK to derive the timing from the clock pulse on a digital trunk connected to the board · OSC to use the board's on-board oscillator. Use only when no other source is available.
Clocking.HBus.ClockSourceNetwork	If Clocking.HBus.ClockSource is set to NETWORK, specifies the board trunk to derive the primary timing reference from (1 to n, where n is the number of trunks on the board). Trunk numbers are zero-based (for example, specify 1 for trunk 0).
Clocking.HBus.AutoFallBack	Enables or disables auto-fallback on the board. When set to YES this keyword specifies that the board automatically switches to the Clocking.HBus.FallBackClockSource timing reference when the Clocking.HBus.ClockSource timing reference fails. The board continues to drive the CT bus clock using this timing reference until the first timing reference is re-established.
Clocking.HBus.FallBackClockSource	Specifies the fallback timing reference for the board to use if the primary timing reference fails. The board continues to drive the CT bus clock using this timing reference until the primary timing reference is re-established. For the primary clock master, set to any of the following: · NETREF to use NETREF(1) · NETREF2 to use NETREF2 (H.110 only) · NETWORK to derive the timing from the clock pulse on a digital trunk connected to the board · OSC to use the board's on-board oscillator. Use only when no other source is available. The fallback timing reference should be different from the primary timing reference.
Clocking.HBus.FallBackNetwork	If Clocking.HBus.FallBackClockSource is set to NETWORK, specifies the board trunk to derive the fallback timing reference from. (1 to n, where n is the number of trunks on the board). Trunk numbers are zero-based (for example, specify 1 for trunk 0).

Configuring the Secondary Clock Master

You can optionally set up a secondary clock master to drive a CT bus clock if the primary clock master stops driving its CT bus clock. Use the following keywords to configure the secondary clock master:

Keyword	Description
Clocking.HBus.ClockMode	Specifies the CT bus clock that the board drives. For the secondary clock master, specify the clock not driven by the primary clock master. For example, if the primary master drives B_CLOCK, specify MASTER_A for this keyword for the secondary master.
Clocking.HBus.ClockSource	Specifies the primary timing reference for the board. For the secondary clock master, set to the CT bus clock driven by the primary master: A_CLOCK or B_CLOCK. This makes the secondary master a slave to the primary master.
Clocking.HBus.AutoFallBack	Enables or disables auto-fallback on the board. For the secondary clock master, set to YES.
Clocking.HBus.FallBackClockSource	Specifies the fallback timing reference for the board, to use if the primary timing reference fails. Once the secondary master is driving the CT bus clock, it continues to drive the clock until software intervention by an application. For the secondary clock master, set to any timing reference not used by the primary clock master: · NETREF to use NETREF1 · NETREF2 to use NETREF2 (H.110 only) · NETWORK to derive the timing from the clock pulse on a digital trunk connected to the board · OSC to use the board's on-board oscillator. Use only when no other source is available.
Clocking.HBus.FallBackNetwork	If Clocking.HBus.FallBackClockSource is set to NETWORK, specifies the board trunk to derive the fallback timing reference from. Trunk numbers are zero-based (for example, specify 0 for trunk 1).

Configuring Clock Slaves

Any board connected to the CT bus that is not the primary or secondary clock master should be configured as a clock slave. Each clock slave derives its primary timing reference from A_CLOCK or B_CLOCK (whichever is driven by the primary clock master).

If you have set up a secondary clock master, when the primary clock master stops driving its CT bus clock, the clock slaves can get their clocking information from the secondary clock master.

Use the following keywords to configure clock slaves:

Keyword	Description
Clocking.HBus.ClockMode	Specifies the CT bus clock that the board drives. For a clock slave, set to SLAVE to indicate that the board does not drive any CT bus clock.
Clocking.HBus.ClockSource	Specifies the primary timing reference for the board. For each slave, set to the CT bus clock driven by the primary master: A_CLOCK or B_CLOCK.
Clocking.HBus.AutoFallBack	Enables or disables auto-fallback on the board. If you have set up a secondary clock master, set to YES for each slave. Otherwise, set to NO.
Clocking.HBus.FallBackClockSource	Specifies the fallback timing reference for the board, to use if the primary timing reference fails. If you have set up a secondary clock master, set to the timing reference driven by the secondary clock master. Once a slave switches to the secondary clock, it continues to use the clock until reset by an application.

Configuring Standalone Boards

If you want to configure a board in standalone mode so that the board references its own timing information, set Clocking.HBus.ClockMode to STANDALONE.

In this mode, the board will not be able to make connections to the CT bus.

With some board models, specifying standalone mode causes certain default switch connections to be made on the board to route incoming information from the trunk to DSP resources. For details, see the board documentation.

Configuring NETREF (NETREF1) and NETREF2

If you have specified that any board will use NETREF (NETREF1) or NETREF2 as a timing reference, you must configure one or two other boards to drive the signals. You should configure a different board for each signal. The source for each signal can be a digital trunk.

Note: NETREF2 is only available in H.110 configurations.

Use the following keywords to configure a board to drive NETREF (NETREF1):

Keyword	Description
Clocking.HBus.NetRefSource	Specifies the source of the NETREF (NETREF1) timing reference. Set to any of the following: · NETWORK to cause the board to drive NETREF based on the signal from a digital trunk connected to the board · STANDALONE if the board will not drive NETREF · OSC to cause the board to drive NETREF using its oscillator (for debugging purposes only)
Clocking.HBus.NetRefSourceNetwork	If Clocking.HBus.NetRefSource is set to NETWORK, specifies the number of the trunk to get the signal from.
Clocking.HBus.NetRefSpeed	Sets the speed of the NETREF signal. 8 kHz is recommended. For details, see your hardware documentation.

Use the following keywords to configure a board to drive NETREF2:

Keyword	Description
Clocking.HBus.NetRef2Source	Specifies the source of the NETREF2 timing reference. Set to any of the following: · OSC to cause the board to drive NETREF2 using its oscillator · NETWORK to cause the board to drive NETREF2 based on the signal from a digital trunk connected to the board · STANDALONE if the board will not drive NETREF2.
Clocking.HBus.NetRef2SourceNetwork	If Clocking.HBus.NetRefSource is set to NETWORK, specifies the number of the trunk to get the signal from.
Clocking.HBus.NetRef2Speed	Sets the speed of the NETREF2 signal. 8 kHz is recommended. For details, see your hardware documentation.

Note: Not all boards can drive NETREF or NETREF2. For details on your board models, refer to your board-specific documentation.

Example: Multi-Board System

The following example describes a system configuration (illustrated in Figure 28), where four boards reside in a single chassis. The boards are configured in the following way:

Board	Description	Drives	Primary timing reference	Fallback timing reference
A	Primary clock master	A_CLOCK	NETREF	Local digital trunk 2
B	Secondary clock master	B_CLOCK	A_CLOCK	Local digital trunk 3
C	Clock slave	Nothing	A_CLOCK	B_CLOCK
D	Clock slave	NETREF based on local digital trunk 4	A_CLOCK	B_CLOCK

Auto-fallback is enabled on all boards. Board A, defined as the primary clock master, drives A_CLOCK. All other boards on the system connected to the CT bus use A_CLOCK as their primary timing reference. Board A derives its own timing reference from the NETREF signal driven by board D, based on a signal from one of board D's digital trunks (trunk 4).

In addition, board A is configured to use timing signals received on one of its own digital trunks (trunk 2) as its fallback timing reference. If NETREF fails, board A continues to drive A_CLOCK based on its fallback timing reference.

Board B is set up as a backup, or secondary clock master, driving the CT bus clock not driven by the primary clock master. Board B normally receives its timing reference from A_CLOCK, which is driven by board A. This means that board B acts as a clock slave to board A. If A_CLOCK fails, board B continues driving B_CLOCK, but now uses the timing signals received from one of its digital trunks (trunk 3). All other slave boards fall back to B_CLOCK, and board B serves as the clock master. The primary master also falls back to B_CLOCK, and is now a slave to the secondary master. The system continues in this configuration until software intervention by the application.

This configuration assigns the following clocking priorities:

Timing Priority	Clocking Configuration
First	Board A (primary master) drives A_CLOCK using its primary timing reference (board D, digital trunk 4, via NETREF). Slaves sync to A_CLOCK.
Second	Board A (primary master) drives A_CLOCK using its fallback timing reference (board A, digital trunk 2). Slaves sync to A_CLOCK.
Third	Board B (secondary master) drives B_CLOCK using its fallback timing reference (board B, digital trunk 3). Slaves sync to B_CLOCK.

Figure 28. Sample Board Clocking Configuration

Clock configuration keywords are set as follows for each board:

Board	Role	Clocking Keyword Settings
A	Primary clock master	Clocking.HBus.ClockMode = MASTER_A Clocking.HBus.ClockSource = NETREF Clocking.HBus.AutoFallBack = YES Clocking.HBus.FallBackClockSource = NETWORK Clocking.HBus.FallBackNetwork = 2
B	Secondary clock master	Clocking.HBus.ClockMode = MASTER_B Clocking.HBus.ClockSource = A_CLOCK Clocking.HBus.AutoFallBack = YES Clocking.HBus.FallBackClockSource = NETWORK Clocking.HBus.FallBackNetwork = 3
C	Clock slave	Clocking.HBus.ClockMode = SLAVE Clocking.HBus.ClockSource = A_CLOCK Clocking.HBus.AutoFallBack = YES Clocking.HBus.FallBackClockSource = B_CLOCK
D	Slave driving NETREF	Clocking.HBus.ClockMode = SLAVE Clocking.HBus.ClockSource = A_CLOCK Clocking.HBus.AutoFallBack = YES Clocking.HBus.FallBackClockSource = B_CLOCK Clocking.HBus.NetRefSource = NETWORK Clocking.HBus.NetRefSourceNetwork = 4 Clocking.HBus.NetRefSpeed = 8K